• Journal of Electrical Engineering and Technology
• /
• v.13 no.6
• /
• pp.2493-2503
• /
• 2018

Passive dynamic walking exhibits humanoid and energy efficient gaits. However, optimal design of passive walker at multi-variable level is not well studied yet. This paper presents a Chaotic Particle Swarm Optimization (CPSO) algorithm and applies it to the optimal design of flexible passive walker. Hip torsional stiffness and damping were incorporated into flexible biped walker, to imitate passive elastic mechanisms utilized in human locomotion. Hybrid dynamics were developed to model passive walking, and period-one gait was gained. The parameters global searching scopes were gained after investigating the influences of structural parameters on passive gait. CPSO were utilized to optimize the flexible passive walker. To improve the performance of PSO, multi-scroll Jerk chaotic system was used to generate pseudorandom sequences, and chaotic disturbance would be triggered if the swarm is trapped into local optimum. The effectiveness of CPSO is verified by comparisons with standard PSO and two typical chaotic PSO methods. Numerical simulations show that better fitness value of optimal design could be gained by CPSO presented. The proposed CPSO would be useful to design biped robot prototype.

• The Journal of the Korea institute of electronic communication sciences
• /
• v.17 no.4
• /
• pp.671-678
• /
• 2022

Approximate computing is an computational technique that is acceptable degree of inaccurate results of accurate results. Approximate multiplication is one of the approximate computing methods for high-performance and low-power computing. In this paper, we propose a high-density, low-power, and high-speed approximate multiplier using approximate 4-2 compressor and improved full adder. The approximate multiplier with approximate 4-2 compressor consists of three regions of the exact, approximate and constant correction regions, and we compared them by adjusting the size of region by applying an efficient partial product reduction. The proposed approximate multiplier was designed with Verilog HDL and was analyzed for area, power and delay time using Synopsys Design Compiler (DC) on a 25nm CMOS process. As a result of the experiment, the proposed multiplier reduced area by 10.47%, power by 26.11%, and delay time by 13% compared to the conventional approximate multiplier.

• IEIE Transactions on Smart Processing and Computing
• /
• v.4 no.3
• /
• pp.133-140
• /
• 2015

Neural stimulating implantable medical devices (IMDs) have been widely used to treat neurological diseases or interface with sensory feedback for amputees or patients suffering from severe paralysis. More recent IMDs, such as retinal implants or brain-computer interfaces, demand higher performance to enable sophisticated therapies, while consuming power at higher orders of magnitude to handle more functions on a larger scale at higher rates, which limits the ability to supply the IMDs with primary batteries. Inductive power transmission across the skin is a viable solution to power up an IMD, while it demands high power efficiencies at every power delivery stage for safe and effective stimulation without increasing the surrounding tissue's temperature. This paper reviews various wireless neural stimulating systems and their power management techniques to maximize IMD power efficiency. We also explore both wireless electrical and optical stimulation mechanisms and their power requirements in implantable neural interface applications.

• Proceedings of the IEEK Conference
• /
• 2002.06b
• /
• pp.101-104
• /
• 2002

This paper propose that is algorithm of power dissipation reduction in the high level synthesis design for DSP(Digital Signal Processor), as the portable terminal system recently demand high power dissipation. This paper obtain effect of power dissipation reduction and switching activity that increase correlation of operands as input data of function unit. The algorithm search loop or repeatedly data to the input operands of function unit. That can be reduce the power dissipation using the new low power high level synthesis algorithm. In this Paper, scheduling operation search same nodes from input DFG(Data Flow Graph) with correlation coefficient of first input node and among nodes. Function units consist a multiplier, an adder and a register. The power estimation method is added switching activity for each bits of nodes. The power estimation have good efficient using proposed algorithm. This paper result obtain more Power reduction of fifty percents after using a new low power algorithm in a function unit as multiplier.

• Journal of the Korea Fashion and Costume Design Association
• /
• v.13 no.1
• /
• pp.59-71
• /
• 2011

As an exaggerated-shoulder becomes a growing trend women's clothing, the crescent shaped sleeve with parallel style lines in the arm hole is a highly used women's sleeve pattern. This study develops and provides an applicable method for making the crescent shaped power shoulder sleeve. An efficient basic method for making the 2 piece crescent shaped sleeve was developed and the sensory appearance test was carried out with experimental clothes. There are two principles for making the crescent shaped sleeve: having a style line in the sleeve and pasting part of the cut arm hole of the bodice to the sleeve. The latter would be more convenient for a 2 piece sleeve, mostly used for jackets. The crescent shaped sleeve used in power shoulder jackets should set the shoulder angle as you wish to extend and raise the shoulder point of the bodice and sleeve to the same height. For a stronger power shoulder image, a 3 piece sleeve has a better appearance. Also, the height of the shoulder has to be enhanced with a shoulder pad for a more stable sleeve.

• ETRI Journal
• /
• v.38 no.5
• /
• pp.941-951
• /
• 2016

In this paper, cognitive radio and simultaneous wireless information and power transfer (SWIPT) are effectively combined to design a spectrum-efficient and energy-efficient transmission paradigm. Specifically, a novel SWIPT-based primary-secondary cooperation model is proposed to increase the transmission rate of energy/spectrum constrained users. In the proposed model, a multi-antenna secondary user conducts simultaneous energy harvesting and information forwarding by means of power splitting (PS), and tries to maximize its own transmission rate under the premise of successfully assisting the data delivery of the primary user. After the problem formulation, joint power splitting and beamforming optimization algorithms for decode-and-forward and amplify-and-forward modes are presented, in which we obtain the optimal PS factor and beamforming vectors using a golden search method and dual methods. Simulation results show that the proposed SWIPTbased primary-secondary cooperation schemes can obtain a much higher level of performance than that of non-SWIPT cooperation and non-cooperation schemes.

• Journal of the Optical Society of Korea
• /
• v.15 no.3
• /
• pp.305-309
• /
• 2011

We present an efficient design approach for a plasmonic slot waveguide using a genetic algorithm. The analyzed structure consists of a nanometric slot in a thin metallic film embedded within a dielectric. To achieve high confinement without long propagation length, the thickness and width of the slot are optimally designed in order to optimize the figures of merit including mode confinement and propagation length. The optimized design is based on the finite element method and enhances the guiding and focusing of light power propagation.

• Nuclear Engineering and Technology
• /
• v.52 no.2
• /
• pp.323-327
• /
• 2020

In this study, the neutronic calculation to obtain tritium breeding ratio (TBR) in a deuterium-tritium (D-T) fusion power reactor using Monte Carlo MCNPX is done. In addition, by using COMSOL software, an efficient cooling system is designed. In the proposed design, it is adequate to enrich up to 40% ⁶Li. Total tritium breeding ratio of 1.12 is achieved. The temperature of helium as coolant gas never exceed 687℃. As regards the tolerable temperature of beryllium (650℃), the design of blanket module is done in the way that beryllium temperature never exceed 600℃. The main feature of this design indicates the temperature of helium coolant is higher than other proposed models for blanket module, therefore power of electricity generation will increase.

• Proceedings of the KIEE Conference
• /
• 1998.07c
• /
• pp.1188-1191
• /
• 1998

Detailed estimation of subsurface resistivity distribution and accurate estimation of actual fault current coming into the grounding system are indispensible to optimun grounding system design. Especially, it is essential for efficient grounding design to estimate subsurface resistivity distribution quantitatively and logically. Accurate estimation of subsurface resistivity distribution has an absolute influence on calculating touch voltage, step voltage and ground potential rise (GPR) which are related with grounding design standard for human safety. In this study, thirty-three electrical sounding surveys were made in Yongdam Power Station to obtain detailed subsurface resistivity distribution and the sounding data were interpreted quantitatively using multi-layered model. The results of the quantitative resistivity models were adopted practically to calculate grounding resistance values. Analytical asymptotic equations and CDEGS program were used in grounding resistance calculation and the results were compared and reviewed in the study.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.25 no.1
• /
• pp.20-26
• /
• 2021

Recent systems contain hardware and software components together for faster execution speed and less power consumption. In conventional hardware and software co-design, the ratio of software and hardware was divided by the designer's empirical knowledge. To find optimal results, designers iteratively reconfigure accelerators and applications and simulate it. Simulating iteratively while making design change is time-consuming. In this paper, we propose a hardware and software co-design platform for energy-efficient FPGA accelerator design. The proposed platform makes it easy for designers to find an appropriate hardware ratio by automatically generating application program code and hardware code by parameterizing the components of the accelerator. The co-design platform based on the Vitis unified software platform runs on a server with Xilinx Alveo U200 FPGA card. As a result of optimizing the multiplication accelerator for two matrices with 1000 rows, execution time was reduced by 90.7% and power consumption was reduced by 56.3%.