• The Transactions of the Korean Institute of Electrical Engineers P
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• v.63 no.4
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• pp.345-350
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• 2014

DC electrolytic capacitor is widely used in the power converter including PWM inverter, switching power supply and PFC Boost converter system because of its large capacitance, small size and low cost. In this paper, basic characteristics of DC electrolytic capacitor vs. frequency is presented and the real-time estimation scheme of ESR and capacitance based on the bandpass filtering is adopted to the single phase boost converter of uninterruptible power supply to diagnose its split dc-link capacitors. The feasibility of this real-time failure prediction monitoring system is verified by the computer simulation of the 5[kW] singe phase PFC half-bridge boost converter.

• ETRI Journal
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• v.43 no.4
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• pp.746-757
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• 2021

Side-channel attacks pose an inevitable challenge to the implementation of cryptographic algorithms, and it is important to mitigate them. This work identifies a novel data encoding technique based on 1-of-4 codes to resist differential power analysis attacks, which is the most investigated category of side-channel attacks. The four code words of the 1-of-4 codes, namely (0001, 0010, 1000, and 0100), are split into two sets: set-0 and set-1. Using a select signal, the data processed in hardware is switched between the two encoding sets alternately such that the Hamming weight and Hamming distance are equalized. As a case study, the proposed technique is validated for the NIST standard AES-128 cipher. The proposed technique resists differential power analysis performed using statistical methods, namely correlation, mutual information, difference of means, and Welch's t-test based on the Hamming weight and distance models. The experimental results show that the proposed countermeasure has an area overhead of 2.3× with no performance degradation comparatively.

• Transactions of the Korean Society of Automotive Engineers
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• v.15 no.5
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• pp.118-124
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• 2007

The efficiency of the hybrid systems which are composed of compound planetary gear sets depend on the amount of the recirculating energy among the motors and battery. This paper studies the analysis of the system efficiency with the parameters, ${\alpha},\;{\beta},\;{\gamma_a},\;{\gamma_b}$ and $\gamma_s$. The efficiency of the systems and the relative torque, speed and power of the power resources are represented by these parameters. The recuperating parameter $\kappa$ which makes the systems generalized is introduced, so the efficiencies of the modes such as the hybrid mode, the engine mode, the motoring mode and the recuperating mode are analyzed with simple equations. The tendency of the system efficiency according to the variations of the $\gamma_s$ and $\kappa$ are studied, by which it can be possible to reduce the loss of the power because the strategies for avoiding the singular speed ratio $\gamma_s$ are helpful for the system efficiency and specific value of $\kappa$ can increase the efficiency of the systems.

• Journal of the Korean Society of Manufacturing Process Engineers
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• v.15 no.5
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• pp.48-56
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• 2016

In this paper, we analyze the power flow of an eight-speed automatic transmission by using a lever analogy for the manufacturing of planetary gears. The results indicate that the engine power is passed down to the carrier and ring gear in the first double pinion planetary gear (DPPG1), and to the sun gear, carrier, and ring gear in DPPG3 for the first speed. Although the power flow is similar in the second speed, the power circulation occurs in the second single pinion planetary gear (SPPG2). For the third speed, the engine power is passed from the carrier to the ring gear in DPPG, at which point the power is split between the sun gears of SPPG2 and DPPG3.

• Journal of Korea Society of Digital Industry and Information Management
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• v.10 no.1
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• pp.1-6
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• 2014

In this paper, we propose a CPLD low power algorithm considering the structure. The proposed algorithm is implemented CPLD circuit FC(Feasible Cluster) for generating a problem occurs when the node being split to overcome the area and power consumption can reduce the algorithm. CPLD to configure and limitations of the LE is that the number of OR-terms. FC consists of an OR node is divided into mainly as a way to reduce the power consumption with the highest number of output nodes is divided into a top priority. The highest number of output nodes with the highest number of switching nodes become a cut-point. Division of the node is the number of OR-terms of the number of OR-terms LE is greater than adding the input and output of the inverter converts the AND. Reduce the level, power consumption and area. The proposed algorithm to MCNC logic circuits by applying a synthetic benchmark experimental results of 13% compared to the number of logical blocks decreased. 8% of the power consumption results in a reduced efficiency of the algorithm represented been demonstrated.

• KEPCO Journal on Electric Power and Energy
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• v.8 no.2
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• pp.159-179
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• 2022

Often a network becomes complex, and multiple entities would get in charge of managing part of the whole network. An example is a utility grid. While the entire grid would go under a single utility company's responsibility, the network is often split into multiple subsections. Subsequently, each subsection would be given as the responsibility area to the corresponding sub-organization in the utility company. The issue of how to make subsystems of adequate size and minimum number of interconnections between subsystems becomes more critical, especially in real-time simulations. Because the computation capability limit of a single computation unit, regardless of whether it is a high-speed conventional CPU core or an FPGA computational engine, it comes with a maximum limit that can be completed within a given amount of execution time. The issue becomes worsened in real time simulation, in which the computation needs to be in precise synchronization with the real-world clock. When the subject of the computation allows for a longer execution time, i.e., a larger time step size, a larger portion of the network can be put on a computation unit. This translates into a larger margin of the difference between the worst and the best. In other words, even though the worst (or the largest) computational burden is orders of magnitude larger than the best (or the smallest) computational burden, all the necessary computation can still be completed within the given amount of time. However, the requirement of real-time makes the margin much smaller. In other words, the difference between the worst and the best should be as small as possible in order to ensure the even distribution of the computational load. Besides, data exchange/communication is essential in parallel computation, affecting the overall performance. However, the exchange of data takes time. Therefore, the corresponding consideration needs to be with the computational load distribution among multiple calculation units. If it turns out in a satisfactory way, such distribution will raise the possibility of completing the necessary computation in a given amount of time, which might come down in the level of microsecond order. This paper presents an effective way to split a given electrical network, according to multiple criteria, for the purpose of distributing the entire computational load into a set of even (or close to even) sized computational loads. Based on the proposed system splitting method, heavy computation burdens of large-scale electrical networks can be distributed to multiple calculation units, such as an RTDS real time simulator, achieving either more efficient usage of the calculation units, a reduction of the necessary size of the simulation time step, or both.

• Journal of Power Electronics
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• v.15 no.5
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• pp.1190-1199
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• 2015

This paper presents a new resonant converter to achieve the soft switching of power devices. Two full-bridge converters are connected in series to clamp the voltage stress of power switches at V_in/2. Thus, power MOSFETs with a 500V voltage rating can be used for 800V input voltage applications. Two flying capacitors are connected on the AC side of the two full-bridge converters to automatically balance the two split input capacitor voltages in every switching cycle. Two resonant tanks are used in the proposed converter to share the load current and to reduce the current stress of the passive and active components. If the switching frequency is less than the series resonant frequency of the resonant tanks, the power MOSFETs can be turned on under zero voltage switching, and the rectifier diodes can be turned off under zero current switching. The switching losses on the power MOSFETs are reduced and the reverse recovery loss is improved. Experiments with a 1.5kW prototype are provided to demonstrate the performance of the proposed converter.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.14 no.1
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• pp.20-39
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• 2020

This paper considers a downlink multi-carrier cooperative non-orthogonal multiple access (NOMA) transmission, where no direct link exists between the far user and the base station (BS), and the communication between them only relies on the assist of the near user. Firstly, the BS sends a superimposed signal of the far and the near user to the near user, and then the near user adopts simultaneous wireless information and power transfer (SWIPT) to split the received superimposed signal into two portions for energy harvesting and information decoding respectively. Afterwards, the near user forwards the signal of the far user by utilizing the harvested energy. A minimum data is required to ensure the quality of service (QoS) of the far user. We jointly optimize power allocation, subcarrier allocation, time allocation, the power allocation (PA) coefficient and the power splitting (PS) ratio to maximize the number of data bits received at the near user under the energy causality constraint, the minimum data constraint and the transmission power constraint. The block-coordinate descent method and the Lagrange duality method are used to obtain a suboptimal solution of this optimization problem. In the final simulation results, the superiority of the proposed NOMA scheme is confirmed compared with the benchmark NOMA schemes and the orthogonal multiple access (OMA) scheme.

• Proceedings of the IEEK Conference
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• summer
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• pp.204-208
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• 2004

Embedded business will be expanded market more and more since customers seek more wearable and ubiquitous systems. Cellular telephones, PDAs, notebooks and portable multimedia devices could bring higher microprocessor revenues and more rewarding improvements in performance and functions. Increasing battery capacity is still creeping along the roadmap. Until a small practical fuel cell becomes available, microprocessor developers must come up with power-reduction methods. According to MPR 2003, the instruction and data caches of ARM920T processor consume $44\%$ of total processor power. The rest of it is split into the power consumptions of the integer core, memory management units, bus interface unit and other essential CPU circuitry. And the relationships among CPU, peripherals and caches may change in the future. The processor working on higher operating frequency will exact larger cache RAM and consume more energy. In this paper, we propose advanced low power trace cache which caches traces of the dynamic instruction stream, and reduces cache access times. And we evaluate the performance of the trace cache and estimate the power of the trace cache, which is compared with conventional cache.

• ETRI Journal
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• v.34 no.6
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• pp.838-846
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• 2012

This paper proposes a cost-effective hybrid-type power budget extender (PBEx) that can provide a high power budget of over 45 dB in an asymmetric 10-Gb/s Ethernet passive optical network (10/1G-EPON). The hybrid-type 10/1G-EPON PBEx comprises a central office terminal (COT) and remote terminal (RT) module supporting four channels and uses a coarse wavelength division multiplexing (CWDM) technology between the COT and RT for a reduction of fiber cost and efficient access network design. The proposed 10/1G-EPON PBEx can provide over a 40-km reach and 128-way split per CWDM wavelength with no modification of a legacy 10/1G-EPON system and can satisfy the error-free service in $10^{10}$ packet transmission.