• Title/Summary/Keyword: power matching

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Inrush Current Control of Matching Transformer for Dynamic Voltage Restorer (동적전압보상기를 위한 정합 변압기의 돌입전류 제어)

  • Seo, Il-Dong;Jeon, Hee-Jong;Shon, Jin-Geun
    • The Transactions of the Korean Institute of Power Electronics
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    • v.11 no.4
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    • pp.340-348
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    • 2006
  • This paper proposes an inrush current control technique of matching transformer for configuration of dynamic voltage restorer(DVR). The DVR system consist of PWM inverter to inject arbitrary voltage, LC low pass filter as harmonic eliminator and matching transformer for isolation. However, the matching transformer has an excess of inrush current by magnetic flux saturation in the core. Due to this inrush current, the rating of matching transformers is double for needed nominal rating for protection of DVR. Therefore, in this paper, the modeling method of magnetic flux saturation is used to analyze a magnitude of inrush current, and additional current controller is used for PWM inverter output regulation. Simulation and experimental results are provided to demonstrate the validity of the proposed control method.

A Study on the Broadband Microwave Amplifier Design Using Potentially Unstable GaAs FET (Potentially Unstable한 GaAs FET를 이용한 광대역 마이크로파증폭기에 관한 연구)

  • Hong, Jae-Pyo;Cho, Young-Ki;Son, Hyon
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.12 no.1
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    • pp.19-26
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    • 1987
  • The broadband microwave amplifier in the 3~4GHz frequency range has been designed by using potentially unstable GaAs FET. Input matching network is designed by 14dB available power gain circles which are in the stable region. In order to obtain maximu, transducer power gain, output matching network which is in the stable region can be designed using Fano's bandpass matching network. The measured values of transducer power gain, $S_11$and $S_22$ show close agreements with the theoretical valuse.

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An Optimized Stacked Driver for Synchronous Buck Converter

  • Lee, Dong-Keon;Lee, Sung-Chul;Jeong, Hang-Geun
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.12 no.2
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    • pp.186-192
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    • 2012
  • Half-rail stacked drivers are used to reduce power consumption of the drivers for synchronous buck converters. In this paper, the stacked driver is optimized by matching the average charging and discharging currents used by high-side and low-side drivers. By matching the two currents, the average intermediate bias voltage can remain constant without the aid of the voltage regulator as long as the voltage ripple stays within the window defined by the hysteresis of the regulator. Thus the optimized driver in this paper can minimize the power consumption in the regulator. The current matching requirement yields the value for the intermediate bias voltage, which deviates from the half-rail voltage. Furthermore the required capacitance is also reduced in this design due to decreased charging current, which results in significantly reduced die area. The detailed analysis and design of the stacked driver is verified through simulations done using 5V MOSFET parameters of a typical 0.35-${\mu}m$ CMOS process. The difference in power loss between the conventional half-rail driver and the proposed driver is less than 1%. But the conventional half-rail driver has excess charge stored in the capacitor, which will be dissipated in the regulator unless reused by an external circuit. Due to the reduction in the required capacitance, the estimated saving in chip area is approximately 18.5% compared to the half-rail driver.

CCP and ICP Combination Impedance Matching Device for Uniformity Improvement of Semiconductor Plasma Etching System (반도체 플라즈마 식각 시스템의 균일도 향상을 위한 CCP와 ICP 결합 임피던스정합 장치)

  • Jung, Doo-Yong;Nam, Chang-Woo;Lee, Jong-Ho;Choi, Dae-Kyu;Won, Chung-Yuen
    • The Transactions of the Korean Institute of Power Electronics
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    • v.15 no.4
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    • pp.274-281
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    • 2010
  • This paper proposes a DFPS (Dual Frequency Power Source) impedance matching device for uniformity improvement of a semiconductor plasma etching system. The DFPS consists of two parts for safe plasma processing on large-area substrates. The first part is an ICP (Inductively Coupled Plasma) for high integration by using ferrite core. The second part is a CCP (Capacitive Coupled Plasma) to control uniformity of whole cells. Proposed DFPS can achieve high productivity improvement required for semiconductor equipment industry. The proposed plasma system is analyzed, simulated and experimentally verified with a matching equipment at 27.12MHz and 400kHz.

The Design and Experiment of Power Factor Improvement Circuit for a Underwater Electro Acoustic Transducer with Low Coupled Dual Resonances (상호 결합이 적은 두 개의 공진점을 갖는 수중용 광대역 전기 음향 변화기를 위한 역률 개선 회로 설계 및 실험)

  • Lim, Jun-Seok;Pyeon, Yong-Guk
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.38B no.12
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    • pp.967-975
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    • 2013
  • In the design of underwater electro acoustic transducer, power factor improvement circuit is more required rather than impedance matching if the driving power amplifier has little inner resistance. Many research results have been focused on the power matching circuit designing for transferring maximum power in the wideband. There are few results in the designing study on the power factor improvement for the wide band underwater electro acoustic transducer. In this paper, we set up a new design method on the power factor improvement for the wide band electro acoustic transducer, and confirm its feasibility by the experiments.

A Fully Integrated 5-GHz CMOS Power Amplifier for IEEE 802.11a WLAN Applications

  • Baek, Sang-Hyun;Park, Chang-Kun;Hong, Song-Cheol
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.7 no.2
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    • pp.98-101
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    • 2007
  • A fully integrated 5-GHz CMOS power amplifier for IEEE 802.11a WLAN applications is implemented using $0.18-{\mu}m$ CMOS technology. An on-chip transmission-line transformer is used for output matching network and voltage combining. Input balun, inter-stage matching components, output transmission line transformer and RF chokes are fully integrated in the designed amplifier so that no external components are required. The power amplifier occupies a total area of $1.7mm{\times}1.2mm$. At a 3.3-V supply voltage, the amplifier exhibits a 22.6-dBm output 1-dB compression point, 23.8-dBm saturated output power, 25-dB power gain. The measured power added efficiency (PAE) is 20.1 % at max. peak, 18.8% at P1dB. When 54 Mbps/64 QAM OFDM signal is applied, the PA delivers 12dBm of average power at the EVM of -25dB.

Optimal Design of Volume Reduction for Capacitive-coupled Wireless Power Transfer System using Leakage-enhanced Transformer (누설집중형 변압기를 이용한 전계결합형 무선전력전송 시스템의 부피저감 최적설계 연구)

  • Choi, Hee-Su;Jeong, Chae-Ho;Choi, Sung-Jin
    • The Transactions of the Korean Institute of Power Electronics
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    • v.22 no.6
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    • pp.469-475
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    • 2017
  • Using impedance matching techniques as a way to increase system power transferability in capacitive wireless power transmission has been widely investigated in conventional studies. However, these techniques tend to increase the circuit volume and thus counterbalance the advantage of the simplicity in the energy link structure. In this paper, a compact circuit topology with one leakage-enhanced transformer is proposed in order to minimize the circuit volume for the capacitive power transfer system. This topology achieves a reactive compensation, and the system quality factor value can be reduced by the turn ratio. As a result, this topology not only reduces the overall system volume but also minimizes the voltage stress of the link capacitor. An optimal design guideline for the leakage-enhanced transformer is also presented. The advantages of the proposed scheme over the conventional method in terms of power efficiency and circuit volume are revealed through an analytic comparison. The feasibility of applying the new topology is also verified by conducting 50 W hardware tests.

Study on matching characteristic according to impedance matching circuit type at MF Frequency band Wireless power transfer (MF 주파수대역 무선전력전송에서 매칭회로타입에 따른 매칭특성에 대한 연구)

  • Kim, Dae-Wook;Yang, Dae-Ki;An, Young-Oh;Lim, Eun-Suk;Choi, Sang-Don;Choi, Dae-Kyu;Chung, Yoon-Do
    • Proceedings of the KIPE Conference
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    • 2014.07a
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    • pp.47-48
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    • 2014
  • 기본적으로 전력전송개념에서 최대의 전력이 전달하기 위해서는 전력전송단과 부하단사이의 임피던스를 맞추어 주어야 최대의 전력이 전달된다. 무선전력전송 역시 RF Source와 송수신 코일간의 임피던스를 맞추어야 최대의 전력전달과 효율을 기대할 수 있다. 따라서 송수신 코일과 부하간에 임피던스 매칭은 필수적으로 필요하다. 매칭이 원할하지 않을 경우 RF Source에 반사전력이 반사되어 심각한 손실을 발생할 수 있으며, 수신부의 부하단에 최대로 전력이 전달되지 않으며 전체 시스템 효율이 나빠지게 된다. 임피던스 매칭회로 타입에는 여러가지 타입이 사용되는데 대표적으로 L type, T Type, ${\pi}$ type이 일반적으로 사용된다. 본 연구에서는 L type, T type, ${\pi}$ type 방식을 이용하여 각 타입별 매칭범위와 매칭특성에 대한 기초실험을 수행하였다.

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Design of a Wide-Frequency-Range, Low-Power Transceiver with Automatic Impedance-Matching Calibration for TV-White-Space Application

  • Lee, DongSoo;Lee, Juri;Park, Hyung-Gu;Choi, JinWook;Park, SangHyeon;Kim, InSeong;Pu, YoungGun;Kim, JaeYoung;Hwang, Keum Cheol;Yang, Youngoo;Seo, Munkyo;Lee, Kang-Yoon
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.16 no.1
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    • pp.126-142
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    • 2016
  • This paper presents a wide-frequency-range, low-power transceiver with an automatic impedance-matching calibration for TV-white-space (TVWS) application. The wide-range automatic impedance matching calibration (AIMC) is proposed for the Drive Amplifier (DA) and LNA. The optimal $S_{22}$ and $S_{11}$ matching capacitances are selected in the DA and LNA, respectively. Also, the Single Pole Double Throw (SPDT) switch is integrated to share the antenna and matching network between the transmitter and receiver, thereby minimizing the systemic cost. An N-path filter is proposed to reject the large interferers in the TVWS frequency band. The current-driven mixer with a 25% duty LO generator is designed to achieve the high-gain and low-noise figures; also, the frequency synthesizer is designed to generate the wide-range LO signals, and it is used to implement the FSK modulation with a programmable loop bandwidth for multi-rate communication. The TVWS transceiver is implemented in $0.13{\mu}m$, 1-poly, 6-metal CMOS technology. The die area of the transceiver is $4mm{\times}3mm$. The power consumption levels of the transmitter and receiver are 64.35 mW and 39.8 mW, respectively, when the output-power level of the transmitter is +10 dBm at a supply voltage of 3.3 V. The phase noise of the PLL output at Band 2 is -128.3 dBc/Hz with a 1 MHz offset.

A 2.65 GHz Doherty Power Amplifier Using Internally-Matched GaN-HEMT (내부정합된 GaN-HEMT를 이용한 2.65 GHz Doherty 전력증폭기)

  • Kang, Hyunuk;Lee, Hwiseob;Lim, Wonseob;Kim, Minseok;Lee, Hyoungjun;Yoon, Jeongsang;Lee, Dongwoo;Yang, Youngoo
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.27 no.3
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    • pp.269-276
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    • 2016
  • This paper presents a 2.65 GHz Doherty power amplifier with internally-matched GaN HEMT. Internal matching circuits were adopted to match its harmonic impedances inside the package. Simultaneously, due to the partially matched fundamental impedance, input and output matching networks become simpler. Bond wires and parasitic elements of transistor package were predicted by EM simulation. For the LTE signal with 6.5 dB PAPR, the implemented Doherty power amplifier shows a power gain of 13.0 dB, a saturated output power of 55.4 dBm, an efficiency of 49.1 %, and ACLR of -26.3 dBc at 2.65 GHz with an operating voltage of 48 V.