• Journal of Power Electronics
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• v.18 no.5
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• pp.1489-1500
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• 2018

Partial shading analysis of large-scale photovoltaic (PV) arrays has recently become a theoretically and numerically challenging issue, and it is necessary for PV system designers. The main contributions of this study are the following: 1) A PSIM-based macro-model was employed because it is remarkably fast, has high precision, and has no convergence issues. 2) Three types of equivalent macro-models were developed for the transformation of a small PV sub-array with uniform irradiance to a new macro-model. 3) On the basis of the proposed new macro-model, a tearing method was established, which can divide a large-scale PV array into several small sub-arrays to significantly improve the efficiency improvement of a simulation. 4) Three platforms, namely, PSIM, PSpice, and MATLAB, were applied to evaluate the proposed tearing method. The proposed models and methods were validated, and the value of this research was highlighted using an actual large-scale PV array with 2420 PV modules. Numerical simulation demonstrated that the tearing method can remarkably improve the simulation efficiency by approximately thousands of times, and the method obtained a precision of nearly 6.5%. It can provide a useful tool to design the optimal configuration of a PV array with a given shading pattern as much as possible.

• JSTS:Journal of Semiconductor Technology and Science
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• v.10 no.1
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• pp.11-19
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• 2010

Register transfer level power macromodeling is well known as a promising technique for accurate and efficient power estimation. This paper proposes effective approaches based on the tablebased method for the RTL power macro-modeling. The new parameter SD, which characterizes the distribution of switching activities for each gate in the circuit, is one of the contributions. The new parameter SD has strong correlation with power consumption. We also propose an accurate table reference method considering the circuit characteristics. The table reference method is applicable for every table-based method and outputs more accurate power value. The experimental results show that the combination of the proposed methods reduces max error 30.36% in the best case, comparing conventional methods. The RMS error is also improved 1.70% in the best case.

• Proceedings of the SAREK Conference
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• 2008.11a
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• pp.584-589
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• 2008

It is known that slab thermal storage which uses concrete slab as thermal material is effective in the load leveling and using the nighttime electric power. The temperature distribution is not constant in plenum in thermal storage time by beams, ducts such as several factor. It is considered that this fact will effect on efficiency of thermal storage and indoor thermal environment. The purpose of this paper is to examine the thermal environment inside plenum. A macro model was made for the analysis of indoor thermal environment as the first step. The flow rate distribution and temperature distribution of object room model was examined by use of basic equations such as airflow by the pressure difference between unit cells, heat flow by air and heat transfer.

• The Transactions of the Korean Institute of Electrical Engineers A
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• v.48 no.10
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• pp.1317-1326
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• 1999

As the integration ratio and operation speed increase, it has become an important problem to estimate the dissipated power during the design procedure as a method to reduce the TTM(time to market). This paper proposed a prediction model to estimate the maximum dissipated power of a CMOS logic gate. This model uses a calculational method. It was formed by including the characteristics of MOSFETs of which a CMOS gate consists, the operational characteristics of the gate, and the characteristics of the input signals. As the modeling process, a maximum power estimation model for CMOS inverter was formed first, and then a conversion model to convert a multiple input CMOS gate into a corresponding CMOS inverter was proposed. Finally, the power model for inverter was applied to the converted result so that the model could be applied to a general CMOS gate. For experiment, several CMOS gates were designed in layout level by $0.6{\mu}m$ layout design rule. The result by comparing the calculated results with those from HSPICE simulations for the gates showed that the gate conversion model has within 5% of the relative error rate to the SPICE and the maximum power estimation model has within 10% of the relative error rate. Thus, the proposed models have sufficient accuracies. Also in calculation time, the proposed models was more than 30 times faster than SPICE simulation. Consequently, it can be said that the proposed model could be used efficiently to estimate the maximum dissipated power of a CMOS logic gate during the design procedure.

• Proceedings of the KIEE Conference
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• 1993.07b
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• pp.781-783
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• 1993

The GTO model is based on the Ebers-Moll equation extened to include the three-junction devices and a detailed description of the implementation of the model equation as well as defferent tests are discussed. Problems to be considered for the snubber design, such as voltage spike reduction, maximum GTO anode current, and switching power, were discussed using the calculation model. The macro model is very useful for simulation of GTO circuit and high power circuit switch in high frequency and complex structure.

• Journal of the Korean Data and Information Science Society
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• v.26 no.6
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• pp.1207-1216
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• 2015

This study aims to compare the model power in developing corporate credit rating models and to suggest a good way to build models based on the characteristic of data. Among many measurement methods, AR is used to measure the model power under various conditions. SAS/MACRO is in use for similar repetitions to reduce time to build models under several combination of conditions. A corporate credit rating model is composed of two sub-models; a credit scoring model and a default prediction model. We verify that the latter performs better than the former under various conditions. From the result of size comparisons, models of large size corporate are more powerful and more meaningful in financial viewpoint than those of small size corporate. As a corporate size gets smaller, the gap between sub-models becomes huge and the effect of outliers becomes serious.

• Proceedings of the KIEE Conference
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• 1999.07c
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• pp.1164-1166
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• 1999

This paper presents Static Synchronous Series Compensator(SSSC) model for power flow study using IPLAN. In the proposed model, SSSC is represented by the equivalent load variation. The equivalent load consists of active power load specified by user and reactive power load which is founded for considering characteristic of SSSC. And this is implemented by IPLAN which is a macro-external program for PSS/E. Using this model, SSSC can be solved in load-flow by just calling the model in PSS/E. The proposed model was applied to a realistic power system for validity test.

• Proceedings of the KIPE Conference
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• 1997.07a
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• pp.148-151
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• 1997

Pspice is not offered a library of mechanical factor like DC Motor, Induction Motor which is needed in Power Electronics field. Therefore, Induction Motor was made library by Equibalent circuit in this study. This model is applied in Voltage-Type inverter and is investigated its characteristics. IGBT is tested by two methods of Macro and Micro Modeling as semiconductor. PWM signal is used of pulse signal. Voltage and current, speed was simulated for assurance of model.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.12
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• pp.55-67
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• 2010

The electrical properties of a back drilled via-hole (BDH) without the open-stub and the plated through via-hole (PTH) with the open-stub, which is called the conventional structure, in a high-count multi~layered (HCML) printed circuit board (PCB) were investigated for a high-speed digital system, and a selected inner layer to transmit a high-speed signal was farthest away from the side to mount the component. Within 10 GHz of the broadband frequency, a design of experiment (DOE) methodology was carried out with three cause factors of each via-hole structure, which were the distance between the via-holes, the dimensions of drilling pad and the anti-pad in the ground plane, and then the relation between cause and result factors which were the maximum return loss, the half-power frequency, and the minimum insertion loss was analyzed. Subsequently, the empirical formulae resulting in a macro model were extracted and compared with the experiment results. Even, out of the cause range, the calculated results obtained from the macro model can be also matched with the measured results within 5 % of the error.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.13 no.5
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• pp.2243-2257
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• 2019

A heterogeneous cellular network (HCN) is useful to increase the spectral and energy efficiency of wireless networks and to reduce the traffic load from the macro cell. The performance of the secondary user equipment (SUE) is affected by interference from the eNodeB (eNB) in a macro cell. To decrease the interference between the macro cell and the small cell, allocating resources properly is essential to an HCN. This study considers the scenario of a software-defined heterogeneous cellular network and performs the resource allocation process. First, we show the system model of HCN and formulate the optimization problem. The optimization problem is a complex process including power and frequency resource allocation, which imposes an extremely high complexity to the HCN. Therefore, a hierarchical resource allocation scheme is proposed, which including subchannel selection and a particle swarm optimization (PSO)-based power allocation algorithm. Simulation results show that the proposed hierarchical scheme is effective in improving the system capacity and energy efficiency.