JSTS:Journal of Semiconductor Technology and Science

  • 제10권1호
  • /
  • Pages.11-19
  • /
  • 2010
  • /
  • 1598-1657(pISSN)
  • /
  • 2233-4866(eISSN)
대한전자공학회 (The Institute of Electronics and Information Engineers)
권호 표지
DOI QR코드

DOI QR Code

A New Approach for Accurate RTL Power Macro-Modeling

  • Kawauchi, Hirofumi (Graduate School of Science and Engineering, Ritsumeikan University) ;
  • Taniguchi, Ittetsu (Graduate School of Science and Engineering, Ritsumeikan University) ;
  • Fukui, Masahiro (Graduate School of Science and Engineering, Ritsumeikan University)
  • 투고 : 2009.09.26
  • 발행 : 2010.03.31
PDF 다운로드
⟨ 이전 논문 다음 논문 ⟩

초록

Register transfer level power macromodeling is well known as a promising technique for accurate and efficient power estimation. This paper proposes effective approaches based on the tablebased method for the RTL power macro-modeling. The new parameter SD, which characterizes the distribution of switching activities for each gate in the circuit, is one of the contributions. The new parameter SD has strong correlation with power consumption. We also propose an accurate table reference method considering the circuit characteristics. The table reference method is applicable for every table-based method and outputs more accurate power value. The experimental results show that the combination of the proposed methods reduces max error 30.36% in the best case, comparing conventional methods. The RMS error is also improved 1.70% in the best case.

키워드

참고문헌

  1. S. Gupta and F.N. Najm, “Analytical model for high level power modeling of combinational and sequential circuits,” Proc. IEEE Alessandro Volta Memorial Workshop on Low-Power Design, pp.164-172, Mar. 1999.
  2. S. Gupta and F.N. Najm, “Power modeling for high-level power estimation,” IEEE Trans. on VLSI systems, Vol.8, No.1, pp.18-29, Feb. 2000. https://doi.org/10.1109/92.820758
  3. G. Bernacchia and M.C. Papaefthymiou, “Analytical macromodeling for high-level power estimation,” Proc. Int. Conf. on Computer-Aided Design, pp.280-283, Nov. 1999.
  4. Y. A. Durrani, T. Riesgo, F. Machado, “Statistical power estimation for resister transfer level,” Proc. Mixed Design of Integrated Circuits and Systems, pp.522-527, Jun. 2006.
  5. M. Ohtsuki, M. Kawai, and M. Fukui, “An efficient algorithm for RTL power macro-modeling and library building,” IEICE Transactions on Electronics, Vol.E92-C, No.4, pp.500-507, Apr. 2009. https://doi.org/10.1587/transele.E92.C.500
  6. M. Anton, I. Colonescu, E. Macii, and M. Poncino, “Fast characterization of RTL power macromodels,” Proc. Int. Conf. on Electronics, Circuits and Systems, pp.1591-1594, Sep. 2001.
  7. F. Klein, G. Araujo, R. Azevedo, R. Leao, and L.C.V. dos Santos, “A multi-model power estimation engine for accuracy optimization,” Proc. Int. Symp. on Low Power Electronics and Design, pp.280-285, Aug. 2007.
  8. H. Kawauchi, T. Morikawa, R. Murashima, I. Taniguchi, and M. Fukui, “A new approach for RTL power macro-modeling,” Proc. Int. Tech. Conf. on Circuits/Systems, Computers and Communications, pp.1025-1027, Jul. 2009.