• Journal of Advanced Marine Engineering and Technology
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• v.13 no.3
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• pp.56-63
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• 1989

In recent years, a.c servo motors have been gradually replacing d.c sevo motors in various high-performance demanded aplications such as machine tools and industrial robots. In particular, the high-performance slip-frequency control of an induction motor, which is often called the vector control, is considered one of the best a.c drive. In this paper, the transient state equation and vector control algrithms of an induction motor are described mathematically by using the two-axis theory(d-q coordinates). According to the result of these algorithms, we scheme the speed control system for an induction type ac servo motor in which vector control is adopted to give tha a.c motor high performance. Motor drive is a PWM inverter using power MOS-FET, and is controlled in order to let the actual input current of the motor track the current reference obtained from a microcomputer(8086 cpu). Driving experiments are performed in the range of 0 to 3000 rpm, and it is verified that high speed response is possible.

• Proceedings of the IEEK Conference
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• 2001.06b
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• pp.129-132
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• 2001

This paper presents an efficient method to estimate the maximum SSN (simultaneous switching noise) for ground interconnection networks in CMOS systems using Taylor's series and analyzes the truncation error that has occurred in Taylor's series approximation. We assume that the curve form of noise voltage on ground interconnection networks is linear and derive a polynomial expression to estimate the maximum value of SSN using $\alpha$-power MOS model. The maximum relative error due to the truncation is shown to be under 1.87% through simulations when we approximate the noise expression in the 3rd-order polynomial.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.34C no.8
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• pp.8-21
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• 1997

In this paper, we consider resistive shorts on gate-source, gate-drain, and drain-source as well as opens in MOS FETs included in typical memory cell of VLSI SRAM and analyze behavior of memory by using PSPICE simulation. Using conventional fault models and this behavioral analysis, we propose linear testing algorithm of complexity O(N) which can be applied to both functional testing and IDDQ (quiescent power supply current) testing simultaneously to improve functionality and reliability of memory. Finally, we implement BIST (built-in self tsst) circuit and BICS(built-in current sensor), which are embedded on memory chip, to carry out functional testing efficiently and to detect various defects at high-speed respectively.

• JSTS:Journal of Semiconductor Technology and Science
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• v.6 no.1
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• pp.38-42
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• 2006

We report 1/f noise PSD(Power Spectrum Density) of sub-100 nm MOSFETs as a function of various parameters such as HCS (Hot Carrier Stress), bias condition, temperature, device size and types of MOSFETs. The noise spectra of sub-100 nm devices showed Lorentzian-like noise spectra. We could check roughly the position of a dominant noise source by changing $V_{DS}$. With increasing measurement temperature, the 1/f noise PSD of 50 nm PMOS device decreases, but there is no decrease in the noise of NMOS device. RTN (Random Telegraph Noise) was measured from the device that shows clearly a Lorentzian-like noise spectrum in 1/f noise spectrum.

• Proceedings of the KIPE Conference
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• 2003.07b
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• pp.750-754
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• 2003

본 논문에서는 X-선 관전류를 직접 검출하여 제어하는 2.4kW(80kv,30mA)급 최소형, 최경량 휴대용 X-선 발생 장치를 제안한다. 본 장치는 X-선발생을 위한 고전압 발생단에 모노탱크 블록 사용하였고, 고주파 고전압용 인버터에는 스위칭 전력소자로서 MOS-FET를 채용, 70kHz로 스위칭 함으로서 고전압 변압기를 비롯한 고전압 발생부의 크기와 무게를 최소화하였다. 또한, 설정 관전류에 대한 정밀한 제어를 위하여 2단계 모드로 필라멘트 예열을 행하여 관전류 응답특성을 개선하였으며 제안한 휴대용 X-선 발생장치의 부하변동에 따른 X-선 관전압과 관전류의 개선된 특징을 실험파형을 통하여 입증하였다.

• 제어로봇시스템학회:학술대회논문집
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• 2000.10a
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• pp.510-510
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• 2000

This paper introduces the design of BiCMOS latched comparator circuit for high-speed system application, which can be used in data conversion, instrumentation, communication system etc. By exploiting the advantage technology of the combination of both the bipolar transistor and the CMOS transistor devices. The comparator circuit includes an input stage that combines MOS sampling with a bipolar regenerative amplifier. The resistive load of conventional current-steering comparator is replaced by a load, which is made by a NMOS transistor. The advantage of design and PSPICE simulation of BiCMOS latched comparator are the circuit will obtain wide bandwidth with lowest power consumption at a single supply voltage. All the characteristics of the proposed BiCMOS latched comparator circuit is carried out by simulation program.

• 제어로봇시스템학회:학술대회논문집
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• 2000.10a
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• pp.512-512
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• 2000

In this article, a current mode peak detector circuit is presented. The simple circuit configuration comprises four MOS transistors and one external capacitor. The realization method is suitable fur fabrication using CMOS technology and all transistors are operated in their saturation region. The proposed circuit exhibits a very low drop rate and provides high accuracy, high-speed and wide dynamic range. The proposed circuit has very low power dissipation and operates using a single 2.5V supply. Simulation results confirmed the characteristic of the proposed circuit are also included.

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.50 no.3
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• pp.115-119
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• 2001

This paper presents an efficient and simple method for analyzine maximum simultaneous switching noise (SSN) on ground interconnection networks in CMOS systems. For the derivation of maximum SSN expression, we use ${\alpha}$-power law MOS model and Taylor's series approximation. The accuracy of the proposed method is verified by comparing the results with those of previous researches and HSPICE simulations under the contemporary process parameters and environmental conditions. The proposed method predicts the maximum SSN values more accurately when compared to existing approaches even in most practical cases such that exist some output drivers not in transition.

• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.489-490
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• 2006

This paper presents a switch type 2.4/5.8 GHz dual band low-noise amplifier, designed with $0.13{\mu}m$ RF CMOS technology. Using MOS switch allows the LNA to have two different input transconductance and output capacitance modes. Given supply voltage of 1.2 V, the simulation exhibits gains of 8.1 dB and 17.1 dB, noise figures of 3.1 dB and 2.57 dB and power consumptions of 13.0 mW and 10.2 mW at 2.4 GHz and 5.8 GHz, respectively.

• Transactions on Electrical and Electronic Materials
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• v.7 no.3
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• pp.103-107
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• 2006

In this paper, a CMOS complementary bridge rectifier for driving RFID transponder chips is presented. The proposed RFID CMOS complementary bridge rectifier is designed with two NMOSs at the input, which are configured by cross-connected gate structures, and two PMOSs and two NMOSs at the output, which are configured by diode-connected MOS structures. Output characteristics of the proposed rectifier are analyzed with the high frequency small-signal equivalent circuit and verified with SPICE for RFID operating frequencies of 13.56 MHz HF for ISO 18000-3, 915MHz UHF for ISO 18000-6, and 2.45 GHz microwave for ISO 18000-4. Simulation results show well-rectified and high enough DC output voltages for driving the low power microchip in the RFID transponder for the frequency range from HF to microwave. DC output voltages are dropped by only around 0.7 V from the input peak-to-peak voltages.