• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1993.11a
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• pp.64-66
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• 1993

The charateristics of low temperature poly-Si thin films with different growth condition were investigated and poly-Si TFTs were fabricated on solid phase crystallized (SPC) amorphous silicon films and as-deposited poly-Si films. The performance of devices fabricated on the SPC amorphous silicon films was shown to be superior to that of devices fabricated on as-deposited poly-Si films. It was found that the characteristics of low-temperature poly-Si thin films such as surface roughness, crystal texture and grain size strongly influenced the poly-Si TFT performance.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.15 no.11
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• pp.969-975
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• 2002

Thin film transistors(TFT) were made based on the polycrystalline Si (poly-Si) crystallized by sequential lateral solidification(SLS) method. The electrical characteristics of the devices were analyzed. n-type TFTs did not show a superior characteristics compared to p-type TFTs. We analyzed the causes of the failure by focused ion beam(FIB) analysis and automatic spreading resistance(ASR) measurement, to study the structural integrity and the doping distribution, respectively. FIB showed no structural problems but it revealed a non-intermixed layer in the contact holes between the polysilicon and the aluminum electrode. ASR analyses on poly-Si layer with various doping concentrations and activation temperatures showed that the inadequately doped areas were partially responsible for the inferior behavior of the whole device.

• Proceedings of the Korean Vacuum Society Conference
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• 2012.02a
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• pp.331-331
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• 2012

With the NAND Flash scaling down, it becomes more and more difficult to follow Moore's law to continue the scaling due to physical limitations. Recently, three-dimensional (3D) flash memories have introduced as an ideal solution for ultra-high-density data storage. In 3D flash memory, as the process reason, we need to use poly-Si TFTs instead of conventional transistors. So, after combining charge trap flash (CTF) structure and poly-Si TFTs, the emerging device SONOS-TFTs has also suffered from some reliability problem such as hot carrier degradation, charge-trapping-induced parasitic capacitance and resistance which both create interface traps. Charge pumping method is a useful tool to investigate the degradation phenomenon related to interface trap creation. However, the curves for charge pumping current in SONOS TFTs were far from ideal, which previously due to the fabrication process or some unknown traps. It needs an optimization and the important geometrical effect should be eliminated. In spite of its importance, it is still not deeply studied. In our work, base-level sweep model was applied in SONOS TFTs, and the nonideal charge pumping current was optimized by adjusting the gate pulse transition time. As a result, after the optimizing, an improved charge pumping current curve is obtained.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.8
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• pp.31-36
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• 2004

we developed a technique to manufacture more reliable polycrystalline silicon TFT-LCDs using UV cleaning and buffered oxide etch(BOE) cleaning which remove the native oxide of the silicon surface before laser annealing. To investigate the effects of pre-treatments on the surface roughness of polycrystalline silicon, we measured atomic force microscopy(AFM). Also the electrical characteristics of polysilicon TFTs, breakdown characteristic and switching Performance, were tested for various pre-treatment conditions and several locations in large glass substrate.

• Proceedings of the KIEE Conference
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• 1998.07d
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• pp.1315-1317
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• 1998

We have investigated the effects of electrical stress on poly-Si TFTs with different hydrogen passivation conditions. The amounts of threshold voltage shift of hydrogen passivated poly-Si TFTs are much larger than those of as-fabricated devices both under the gate bias stressing and under the gate and drain bias stressing. Also, we have quantitatively analized the degradation phenomena using by analytical method. we have suggested that the electron trapping in the gate dielectric is the dominant degradation mechanism in only gate bias stressed poly-Si TFT while the creation of defects in the poly-Si is prevalent in gate and drain bias stressed device.

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.48 no.5
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• pp.367-372
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• 1999

We have investigated the effects of electrical stress on poly-Si TFTs with different hydrogen passivation conditions. The amounts of threshod voltage shift of hydrogen passivated poly-Si TFTs are much larger than those of as-fabricated devices both under the gate only and the gate and drain bias stressing. Also, we have quantitatively analyzed the degradation phenomena by analytical method. We have suggested that the electron trapping in the gate dielectric is the dominant degradation mechanism in only gate bias stressed poly-Si TFT while the creation of defects in the channel region and $poly-Si/SiO_2$ interface is prevalent in gate and drain bias stressed device.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.35D no.12
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• pp.68-74
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• 1998

Improved performance and suppressed short-channel effects of polysilicon thin film transistors (poly-Si TFTs) with very thin electron cyclotron resonance (ECR) $N_2$O-plasma gate oxide have been investigated. Poly-Si TFTs with ECR $N_2$O-plasma oxide ($N_2$O-TFTs) show better performance as well as suppressed short-channel effects than those with conventional thermal oxide. The fabricated $N_2$O-TFTs do not show threshold voltage reduction until the gate length is reduced to 3 ${\mu}{\textrm}{m}$ for n-channel and 1 ${\mu}{\textrm}{m}$ for p-channel, respectively. The improvements are due to the smooth interface, passivation effects, and strong Si ≡ N bonds.

• 한국정보디스플레이학회:학술대회논문집
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• 2004.08a
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• pp.1258-1261
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• 2004

Degradation phenomenon in the low-temperature polysilicon (LTPS) thin-film transistors (TFTs) with different junction structures was investigated. A gate-overlapped lightly doped drain (GOLDD) structure showed better hot-carrier stress (HCS) stability than a conventional LDD one. On the other hand, high drain current stress (HDCS) at $V_{gs}$ = $V_{ds}$ conditions caused much severe device degradation in the GOLDD structure because of its higher current level resulting in the higher applied power. It is suggested that self-heating-induced mobility degradation in the GOLDD TFFs be suppressed for using this structure in short-channel devices.

• Proceedings of the KIEE Conference
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• 1997.07d
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• pp.1475-1477
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• 1997

We have fabricated a novel LDD structured polysilicon thin film transistor with a simple fabrication process, compared with the conventional LDD poly-Si TFT, without LDD implantation by employing taper etched $SiO_2$ film instead of LDD implant mask. The leakage current of the novel LDD device is reduced significantly in OFF state while keeping the ON current to be almost identical to that of the non-LDD poly-Si TFTs.

• Proceedings of the KIEE Conference
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• 1995.07c
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• pp.1085-1087
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• 1995

A large leakage current may be one of the critical issues for poly-silicon thin film transistors(poly-Si TFTs) for LCD applications. In order to reduce the leakage current of poly-Si TFTs, several offset gated structures have been reported. However, those devices, where the offset length in the source region is not same as that in the drain region, exhibit the asymmetric electrical performances such as the threshold voltage shift and the variation of the subthreshold slope. The different offset length is caused by the additional mask step for the conventional offset structures. Also the self-aligned implantation may not be applicable due to the mis-alignment problem. In this paper, we propose a new fabrication method for poly-Si TFTs with a self-aligned offset gated structure by employing a photo resistor reflow process. Compared with the conventional poly-Si TFTs, the device is consist of two gate electrodes, of which one is the entitled main gate where the gate bias is employed and the other is the entitled subgate which is separate from both sides of the main gate. The poly-Si channel layer below the offset oxide is protected from the injected ion impurities for the source/drain implantation and acts as an offset region of the proposed device. The key feature of our new device is the offset lesion due to the offset oxide. Our experimental results show that the offset region, due to the photo resistor reflow process, has been successfully obtained in order to fabricate the offset gated poly-Si TFTs. The advantages of the proposed device are that the offset length in the source region is the same as that in the drain region because of the self-aligned implantation and the proposed device does not require any additional mask process step.