• 대한전자공학회논문지
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• 제23권3호
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• pp.370-375
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• 1986

In this paper, modeling of the conduction mechanism of ion implanted p-type polycrystalline silicon is studied. From this modeling, the resistivity of p-type polycrystalline and its dependence on dopant concentration are calculated. The proposed modeling whose grain size is about 1450 \ulcorneris shwon to agree well with the experimental result.

• 한국신재생에너지학회:학술대회논문집
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• 한국신재생에너지학회 2010년도 춘계학술대회 초록집
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• pp.96.2-96.2
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• 2010

The surface morphology and structural properties of polycrystalline silicon (poly-Si) films made in-situ aluminum induced crystallization at various substrate temperature (300~600) was investigated. Silicon films were deposited by hot-wire chemical vapor deposition (HWCVD), as the catalytic or pyrolytic decomposition of precursor gases SiH4 occurs only on the surface of the heated wire. Aluminum films were deposited by DC magnetron sputtering at room temperature. continuous poly-Si films were achieved at low temperature. from cross-section TEM analyses, It was confirmed that poly-Si above $450^{\circ}C$ was successfully grown on and poly-Si films had (111) preferred orientation. As substrate temperature increases, Si(111)/Si(220) ratio was decreased. The electrical properties of poly-Si film were investigated by Hall effect measurement. Poly-Si film was p-type by Al and resistivity and hall effect mobility was affected by substrate temperature.

• 한국결정성장학회지
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• 제3권1호
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• pp.59-65
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• 1993

저항가열식 고진공증착기를 이용하여 압력센서로 사용될 수 있는 boron이 첨가된 다결정 silicon 박막이 제조되었다. 다결정 silicon 박막은 여러온도에서 quartz 기판위에 증착되었으며, boron은 BN 웨이퍼를 사용하여 확산로에서 doping하였다. $500^{\circ}C$의 기판온도에서 증착된 silicon 박막은 비정질이었으며, $600^{\circ}C$에서 결정을 보이기 시작하였고, $700^{\circ}C$에서 다결정이 되었다. $900^{\circ}C$에서 10분동안 boron을 dopion한 후, 박막의 비저항은 $0.1{\Omega}cm~1.5{\Omega}cm$의 범위에 있었으며, boron 밀도(농도)는 $9.4$\times$10^{15}~2.1$\times${10}^{17}cm^{-3}$이었고, 입자의 크기는 $107{\AA}~191{\AA}$이었다.

• 한국정밀공학회:학술대회논문집
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• 한국정밀공학회 2009년도 춘계학술대회 논문집
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• pp.95-96
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• 2009

• 한국전기전자재료학회논문지
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• 제31권2호
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• pp.74-79
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• 2018

In this report, the results of a systematic study on the effects of polycrystalline silicon gate depletion on the reliability characteristics of metal-oxide semiconductor field-effect transistor (MOSFET) devices were discussed. The devices were fabricated using standard complimentary metal-oxide semiconductor (CMOS) processes, wherein phosphorus ion implantation with implant doses varying from $10^{13}$ to $5{\times}10^{15}cm^{-2}$ was performed to dope the polycrystalline silicon gate layer. For implant doses of $10^{14}/cm^2$ or less, the threshold voltage was increased with the formation of a depletion layer in the polycrystalline silicon gate layer. The gate-depletion effect was more pronounced for shorter channel lengths, like the narrow-width effect, which indicated that the gate-depletion effect could be used to solve the short-channel effect. In addition, the hot-carrier effects were significantly reduced for implant doses of $10^{14}/cm^2$ or less, which was attributed to the decreased gate current under the gate-depletion effects.

• 한국전기전자재료학회논문지
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• 제17권2호
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• pp.121-126
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• 2004

In this paper, the effects of the ozone oxidation of the landing polycrystalline silicon on the cell contact resistance of the DRAM device were studied. For this study, the ozone oxidation of the landing polycrystalline silicon layer was performed under various conditions, which was followed by the normal DRAM processes. Then, the cell contact resistance and $t_{WR}$ (write recovery time) of the devices were measured and analyzed. The experimental results showed that the cell contact resistance was more significantly increased for higher temperature of oxidation, longer time of oxidation, and higher concentration of ozone in the oxidation furnace. In addition, the TEM cross-sectional micrographs clearly showed that the oxide layer at the interface between the landing polycrystalline silicon layer and the plug polycrystalline silicon layer was increased by the ozone oxidation. Furthermore, the rate of the device failure due to too large write recovery time was also found to be well correlated with the increase of the cell contact resistance.

• 분석과학
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• 제24권2호
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• pp.105-112
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• 2011

태양전지용 박막 규소나 차세대 반도체용 박막트랜지스터의 원료로 사용 가능한 하이드로폴리실란의 합성과 물성 분석에 관한 연구이다. 이러한 하이드로폴리실란을 유기 치환기가 없는 사염화규소를 사용하여 합성한 것이 가장 큰 특징이며, 일반적으로 알칼리금속을 사용한 환원법으로 유기용매에 가용성인 하이드로폴리실란을 합성하는 최적 조건을 확립하고자 하였으며 하이드로폴리실란 용액은 그 물성을 여러 가지 분석 방법을 사용하여 조사하였으며 또한 열분해 실험을 통해 무정형 또는 다결정성 규소로 전환시킬 수 있음을 확인하였다.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2004년도 Asia Display / IMID 04
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• pp.129-134
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• 2004

The development of fabrication processes of polycrystalline-silicon-thin-film transistors (poly-Si TFTs) at low temperatures is reviewed. Rapid crystallization through laser-induced melt-regrowth has an advantage of formation of crystalline silicon films at a low thermal budget. Solid phase crystallization techniques have also been improved for low temperature processing. Passivation of $SiO_2$/Si interface and grain boundaries is important to achieve high carrier transport properties. Oxygen plasma and $H_2O$ vapor heat treatments are proposed for effective reduction of the density of defect states. TFTs with high performance is reported.

• 한국결정성장학회지
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• 제4권2호
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• pp.111-118
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• 1994

Crystal growth chamber 상부에 있는 reservoir에서 polycrystalline silicon powder를 연속적으로 feeding하면서 도가니 하부에 용융대를 형성시키고 seed를 meed를 dipping하여 회전시키면서 하부로 끌어내려 단결정을 성장시키는 연속성장법의 기본 원리를 확립하였고, 직접 고안 설계 제작한 연속성장 장치로 silicon 단결정을 성장시켰다. 본 연속성장법은 melt에 미치는 중력, 진동, melt의 표면장력, melt와 solid의 계면 장력, seed의 회전에 따른 원심력 등의 힘들이서로 상쇄되고 power, feeding양과 성장속도가 비례하여 적당한 조합을 이룰 때 안정한 연속성장을 할 수있다.

• 한국재료학회지
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• 제16권9호
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• pp.571-577
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• 2006

We fabricated thermal evaporated 10 nm-Ni/(poly)Si and 10 nm-Ni/1 nm-Ir/(poly)Si films to investigate the thermal stability of nickel monosilicide at the elevated temperatures by rapid annealing them at the temperatures of $300{\sim}1200^{\circ}C$ for 40 seconds. Silicides for salicide process was formed on top of both the single crystal silicon actives and the polycrystalline silicon gates. A four-point tester is used for sheet resistance. Scanning electron microscope and field ion beam were employed for thickness and microstructure evolution characterization. An x-ray diffractometer and an auger depth profile scope were used for phase and composition analysis, respectively. Nickel silicides with iridium on single crystal silicon actives and polycrystalline silicon gates showed low resistance up to $1200^{\circ}C$ and $800^{\circ}C$, respectively, while the conventional nickel monosilicide showed low resistance below $700^{\circ}C$. The grain boundary diffusion and agglomeration of silicides led to lower the NiSi stable temperature with polycrystalline silicon substrates. Our result implies that our newly proposed Ir added NiSi process may widen the thermal process window for nano CMOS process.