• The Transactions of the Korean Institute of Electrical Engineers P
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• v.52 no.1
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• pp.14-19
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• 2003

The effect of the Pt electrode and the $Pt-IrO_2$ hybrid electrode on the performance of ferroelectric device was investigated. The modified Pt thin films with non-columnar structure significantly reduced the oxidation of TiN diffusion barrier layer, which rendered it possible to incorporate the simple stacked structure of Pt/TiN/poly-Si plug. When a $Pt-IrO_2$ hybrid electrode is applied, PZT thin film properties are influenced by the thickness and the partial coverage of the electrode layers. The optimized $Pt-IrO_2$ hybrid electrode significantly enhanced the fatigue properties of the PZT thin film with minimal leakage current.

• Transactions on Electrical and Electronic Materials
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• v.11 no.6
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• pp.257-260
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• 2010

Zinc oxide (ZnO) bottom-contact thin-film transistors (TFTs) were prepared by the use of injector type atomic layer deposition. Two hybrid gate oxide systems of different polarity polymers with silicon oxide were examined with the aim of improving the properties of the transistors. The mobility and threshold voltage of a ZnO TFT with a poly(4-dimethylsilyl styrene) (Si-PS)/silicon oxide hybrid gate dielectric had values of 0.41 $cm^2/Vs$ and 24.4 V, and for polyimide/silicon oxide these values were 0.41 $cm^2/Vs$ and 24.4 V, respectively. The good hysteresis property was obtained with the dielectric of hydrophobicity. The solid output saturation behavior of ZnO TFTs was demonstrated with a $10^6$ on-off ratio.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.33A no.3
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• pp.96-106
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• 1996

One of the major problems for poly-Si TFTs is the large off state leakage current. LDD (lightly doped drain) and offset gated structures have been employed in order to reduce the leakage current. However, these structures also redcue the oN current significantly due to the extra series resistance caussed by the LDD or offset region. It is desirable to have a device which would have the properties of the offset gated structure in the OFF state, while behaving like a fully gated device in the oN state. Therefore, we propose a new thin film transistor with pnp junction gate which reduce the leakage curretn during the OFF state without sacrificing the ON current during the ON state.

• The Transactions of the Korean Institute of Electrical Engineers
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• v.45 no.4
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• pp.568-573
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• 1996

The amorphous silicon films deposited by low pressure chemical vapor deposition are crystallized by the various annealing techniques including low-temperature furnace annealing and two-step annealing. Two-step annealing is the combination of furnace annealing at 600 [.deg. C] for 24 h and the sequential furnace annealing at 950 [.deg. C] 1h or the excimer laser annealing. It s found that two-step annealings reduce the in-grain defects significantly without changing the grain boundary structure. The performance of the poly-Si thin film transistors (TFTs) produced by employing the tow-step annealing has been improved significantly compared with those of one-step annealing. (author). 13 refs., 6 figs., 1 tab.

• Journal of Integrative Natural Science
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• v.4 no.4
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• pp.311-314
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• 2011

Application of self-assembled monolayers (SAMs) to the fabrication of organic thin film transistor has been recently reported very often since it can help to provide ohmic contact between films as well as to form simple and effective electrode pattern. Accordingly, quality of these ultra-thin films is becoming more imperative. In this study, in order to manufacture a high quality SAM pattern, a hydrophobic alkylsilane monolayer and a hydrophilic aminosilane monolayer were selectively coated on $SiO_2$ surface through the consecutive procedures of a micro-contact printing (${\mu}CP$) and dip-coating methods under extremely dry condition. On a SAM pattern cleaned with SC1 solution immediately after ${\mu}CP$, poly(3,4-ethylenedioxythiophene) (PEDOT) source and drain electrode array were very selectively and nicely vapour phase polymerized. On the other side, on a SC1-untreated SAM pattern, PEDOT array was very poorly polymerized. It strongly suggests that the SC1 cleaning process effectively removes unwanted contaminants on SAM pattern, thereby resulting in very selective growth of PEDOT electrode pattern.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.8
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• pp.17-24
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• 2004

Quantum effects in the poly-gate are analyzed in two dimensions using the density-gradient method, and their impact on the short-channel effect of double-gate MOSFETs is investigated. The 2-D effects of quantum mechanical depletion at the gate to sidewall oxide is identified as the cause of large charge-dipole formation at the corner of the gate. The bias dependence of the charge dipole shows that the magnitude of the dipole peak-value increases in the subthreshold region and there is a large difference in carrier and potential distribution compared to the classical solution. Using evanescent-nude analysis, it is found that the quantum effect in the poly-gate substantially increases the short-channel effect and it is more significant than the quantum effect in the Si film. The penetration of potential contours into the poly-gate due to the dipole formation at the drain side of the gate corner is identified as the reason for the substantial increase in short-channel effects.

• Journal of the Korean Institute of Telematics and Electronics
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• v.19 no.1
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• pp.9-13
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• 1982

The purpose of this experiment is to evaluate the noise dependency on the gate dimensions of the P-ch MOSFET which is fabricated of p+ sourse, drain, and gate electrode doped with PH$_3$ gas in type-N Si sudstrate. Experimental results indicate that: for the constant gate area and reletively thick films, noise level tends to decrease for the W/L ratio over unity, which generally conforms with theoretical observations, but its variation with the change in the thickness of film is less than the theoretically predicted for the W/L ratio below unity.

• Proceedings of the KIEE Conference
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• 2002.11a
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• pp.134-136
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• 2002

유리기판 위에서 제작된 다결정 실리콘 TFT(Thin Film Transistor) 에서는 열전도율이 낮은 실리콘 산화막 같은 물질이 사용되기 때문에 열에 대해서 낮은 임계점을 갖는다. 이로 인하여. 게이트와 드레인에 높은 전압이 걸리는 조건에서 동작시킬 경우에는 다결정 실리콘 TFT에서의 열화 현상이 두드러지게 나타나게 된다. 그러나, 열전도율이 실리콘 산화막(SiO2) 보다 열배 이상 높은 실리콘 질화막(SiNx)을 ILD(inter-layer dielectric) 재료로 사용했을 때 같은 스트레스 조건에서 다결정 실리콘의 신뢰성이 개선되는 것을 확인할 수 있었다.

• Journal of Information Display
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• v.11 no.1
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• pp.21-23
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• 2010

A new level shifter using low-temperature polycrystalline silicon (poly-Si) thin-film transistors (TFTs) for low-power applications is proposed. The proposed level shifter uses a capacitive-coupling effect and can reduce the power consumption owing to its no-short-circuit current. Its power saving over the conventional level shifter is 72% for a 3.3 V input and a 10 V output.

• Proceedings of the Korean Vacuum Society Conference
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• 2002.06a
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• pp.79-80
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• 2002