• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.23 no.5
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• pp.353-357
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• 2010

Recently, silicon etching have received much attention for display industry, nano imprint technology, silicon photonics, and MEMS application. After the etching process, removing of etch mask and residue of sidewall is very important. The investigation of the etched mask removing was carried out by using the ashing, HF dipping and acid cleaning process. Experiment shows that oxygen component of reactive gas and photoresist react with silicon and converting them into the mask fence. It is very difficult to remove by using ashing or acid cleaning process because mask fence consisted of Si and O compounds. However, dilute HF dipping is very effective process for SiOx layer removing. Finally, we found optimized condition for etched mask removing.

• Transactions of the Korean Society of Mechanical Engineers A
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• v.31 no.1 s.256
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• pp.50-54
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• 2007

Nickel nano and microstructures are fabricated with simple process. The fabrication process consists of nickel deposition, lithography, nickel ion etching and plasma ashing. Well-aligned nickel nanowalls and nickel self-encapsulated microchannels were fabricated. We found that the ion etching condition as a key fabrication process of nickel nanowalls and self-encapsulated microchannels, i.e., 40 sccm Ar flow, 550 W RF power, 15 mTorr working pressure, and $20^{\circ}C$ water cooled platen without using He backside cooling unit and with using it, respectively. We present the experimental results and discuss the formational conditions and the effect of nickel redeposition on the fabrication of nickel nano and microstructures.

• Proceedings of the Korean Vacuum Society Conference
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• 2014.02a
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• pp.237.1-237.1
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• 2014

Etching is one of the most important steps in semiconductor manufacturing. In etch process control a critical task is to stop the etch process when the layer to be etched has been removed. If the etch process is allowed to continue beyond this time, the material gets over-etched and the lower layer is partially removed. On the other hand if the etch process is stopped too early, part of the layer to be etched still remains, called under-etched. Endpoint detection (EPD) is used to detect the most accurate time to stop the etch process in order to avoid over or under etch. The goal of this research is to develop a hardware and software system for EPD. The hardware consists of an Optical Plasma Monitor (OPM) sensor which is used to continuously monitor the plasma optical emission intensity during the etch process. The OPM software was developed to acquire and analyze the data to perform EPD. Our EPD algorithm is based on the following theory. As the etch process starts the plasma generated in the vacuum is added with the by-products from the etch reactions on the layer being etched. As the endpoint reaches and the layer gets completely removed the plasma constituents change gradually changing the optical intensity of the plasma. Although the change in optical intensity is not apparent, the difference in the plasma constituents when the endpoint has reached leaves a unique signature in the data gathered. Though not detectable in time domain, this signature could be obscured in the frequency spectrum of the data. By filtering and analysis of the changes in the frequency spectrum before and after the endpoint we could extract this signature. In order to do that, first, the EPD algorithm converts the time series signal into frequency domain. Next the noise in the frequency spectrum is removed to look for the useful frequency constituents of the data. Once these useful frequencies have been selected, they are monitored continuously in time and using a sub-algorithm the endpoint is detected when significant changes are observed in those signals. The experiment consisted of three kinds of etch processes; ashing, SiO2 on Si etch and metal on Si etch to develop and evaluate the EPD system.

• Journal of the Korean Vacuum Society
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• v.6 no.2
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• pp.103-108
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• 1997

Silicon field emitter arrays (FEAs) have been fabricated by a novel method employing a two-step tip etch and a spin-on-glass (SOG) etch-back process using double layered thermal/tetraethylortho-silicate (TEOS) oxides as a gate dielectric. A partial etching was performed by coating a low viscous photo resist and $O_2$ plasma ashing on order to form the double layered gate dielectric. A small gate aperture with low gate leakage current was obtained by the novel process. The hight and the end radius of the fabricated emitter was about 1.1 $\mu\textrm{m}$ and less than 100$\AA$, respectively. The anode emission current from a 256 tips array was turned-on at a gate voltage of 40 V. Also, the gate current was less than 0.1% of the anode current.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.28A no.11
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• pp.902-909
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• 1991

A reproducible selective dry etch process of GaAs/AlGaAs Heterostructures for High Electron Mobility Transistor(HEMT) Device fabrication is developed. Using RIE mode with $CCl_{2}F_{2}$ as the basic process gas, the observed etch selectivity of GaAs layer with respect to GaAs/$Al_{0.3}Ga_{0.7}$As is about 610:1. Severe polymer deposition problem, parialy generated from the use of $CCl_{2}F_{2}$ gas only, has been significantly reduced by adding a small amount of He gas or by $O_{2}$ plasma ashing after etch process. In order to obtain an optimized etch process for HEMT device fabrication, we com pared the properties of the wet etched Schottky contact with those of the dry etched one, and set dry etch condition to approach the characteristics of Schottky diode on wet etched surface. By applying the optimized etch process, the fabricated HEMT devices have the maximum transconductance $g_{mext}$ of 224 mS/mm, and have relatively uniform distribution across the 2inch wafer in the value of 200$\pm$20mS/mm.

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.49 no.8
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• pp.487-494
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• 2000

This paper describes the design, fabrication and experiments of surface-micromachined aluminum micromirror array with hidden pin-joints. Instead of the conventional elastic spring components as connection between mirror plate and supporting structure, we used pin-joint composed of pin and staples to support the mirror plate. The placement of pin-joint under the mirror plate makes large active surface area possible. These flexureless micromirrors are driven by electrostatic force. As the mirror plate has discrete deflection angles, the device can be ap;lied to adaptive optics and digitally-operating optical applications. Four-level metal structural layers and semi-cured photoresist sacrificial layers were used in the fabrication process and sacrificial layers were removed by oxygen plasma ashing. Static characteristics of fabricated samples were measured and compared with modeling results.

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.53 no.10
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• pp.546-550
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• 2004

Two fabrication approaches are proposed to planarize the sacrificial layer over hollow structures. One is the photoresist filling method that makes use of photolithography, thermal curing and plasma ashing. The other is the lamination method that is applying pressure and temperature to the organic film over the hollow structures. The fabrication results are compared with those of CMP process. Trenches and cavities with various dimensions have been made for the porposed process. Upon measuring the planarization levels, they are dependent on planarization methods and the geometrical size of hollow structures. The photoresist filling method is so strongly dependent on the width and depth of trenches that we have problems to use it for large dimensional trenches. To the contrary, the flatness of sacrificial layer over the trenches was found to be almost independent of trench dimensions for the lamination method. A CMP process shows the most excellent results, but the fabrication is complicated and the access to it is not so easy. It is important to choose the proper planarization method by considering the required flatness levels, materials to be planarized, and connection between the planarization step and the previous or the following process of it.

• Journal of Sensor Science and Technology
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• v.24 no.6
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• pp.379-384
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• 2015

An infrared image sensor is a core device in a thermal imaging system. The fabrication method of a focal plane array (FPA) is a key technology for a high resolution infrared image sensor. Each pixels in the FPA have $Si_3N_4/SiO_2$ membranes including legs to deposit bolometric materials and electrodes on Si readout circuits (ROIC). Instead of polyimide used to form a sacrificial layer, the feasibility of an amorphous silicon (${\alpha}-Si$) was verified experimentally in a $8{\times}8$ micro-bolometer array with a $50{\mu}m$ pitch. The elimination of the polyimide sacrificial layer hardened by a following plasma assisted deposition process is sometimes far from perfect, and thus requires longer plasma ashing times leading to the deformation of the membrane and leg. Since the amorphous Si could be removed in $XeF_2$ gas at room temperature, however, the fabricated micro-bolomertic structure was not damaged seriously. A radio frequency (RF) sputtered nickel oxide film was grown on a $Si_3N_4/SiO_2$ membrane fabricated using a low stress silicon nitride (LSSiN) technology with a LPCVD system. The deformation of the membrane was effectively reduced by a combining the ${\alpha}-Si$ and LSSiN process for a nickel oxide micro-bolometer.

• JSTS:Journal of Semiconductor Technology and Science
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• v.1 no.2
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• pp.132-139
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• 2001

We considered the uniformity of fabricated micromirror arrays by characterizing the fabrication process and calculating the appropriate driving voltages of micromirrors used as virtual photomask in maskless photolithography. The uniformity of the micromirror array in terms of driving voltage and optical characteristics is adversely affected by factors, such as the air gap between the bottom electrode and the mirror plate, the spring shape and the deformation of the mirror plate or torsion spring. The thickness deviation of the photoresist sacrificial layer, the misalignment between mirror plate and bottom electrode, the aluminum deposition condition used to produce the spring and the mirror plate, and initial mirror deflection were identified as key factors. Their importance lies in the fact that they are related to air gap deviations under the mirror plate, asymmetric driving voltages in left and right mirror directions, and the deformation of the Al sring or mirror plate after removal of the sacrificial layer. The plasma ashing conditions used for removing the sacrificial layer also contributed to the deformation of the mirror plate and spring. Driving voltages were calculated for the pixel operation of the micromirror array, and the non-uniform characteristics of fabricated micromirrors were taken into consideration to improve driving performance reliability.

• Journal of the Microelectronics and Packaging Society
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• v.12 no.3 s.36
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• pp.197-205
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• 2005

Development of the packaging is one of the critical issues for commercialization of the RF-MEMS devices. RF MEMS package should be designed to have small size, hermetic protection, good RF performance and high reliability. In addition, packaging should be conducted at sufficiently low temperature. In this paper, a low temperature hermetic wafer level packaging scheme for the RF-MEMS devices is presented. For hermetic sealing, Au-Sn eutectic bonding technology at the temperature below $300{\times}C$ is used. Au-Sn multilayer metallization with a square loop of $70{\mu}m$ in width is performed. The electrical feed-through is achieved by the vertical through-hole via filled with electroplated Cu. The size of the MEMS Package is $1mm\times1mm\times700{\mu}m$. By applying $O_2$ plasma ashing and fabrication process optimization, we can achieve the void-free structure within the bonding interface as well as via hole. The shear strength and hermeticity of the package satisfy the requirements of MIL-STD-883F. Any organic gases or contamination are not observed inside the package. The total insertion loss for the packaging is 0.075 dB at 2 GHz. Furthermore, the robustness of the package is demonstrated by observing no performance degradation and physical damage of the package after several reliability tests.