• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.13 no.10
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• pp.812-816
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• 2000

It is very important to understand the correlation of between inter dielectric(ILD) CMP process and various facility factors supplied to equipment to equipment system. In this paper, the correlation between the various facility factors supplied to CMP equipment system and ILD-CMP process was studied. To prevent the partial over-polishing(edge hot-spot) generated in the wafer edge area during polishing, we analyze various facilities supplied at supply system. With facility shortage of D.I water(DIW) pressure, we introduced an adding purified $N_2$(P$N_2$)gas in polishing head cleaning station for increasing a cleaning effect. DIW pressure and P$N_2$gas factors were not related with removal rate, but edge hot-spot of patterned wafer had a serious relation. We estimated two factors (DIW pressure and P$N_2$gas) for the improvement of CMP process. Especially, we obtained a uniform planarity in patterned wafer and prohibited more than 90% wafer edge over-polishing. In this study, we acknowledged that facility factors supplied to equipment system played an important role in ILD-CMP process.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2002.11a
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• pp.21-26
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• 2002

Solder flip chip bumping and subsequent coining processes on PCB were investigated to solve the warpage problem of organic substrates for high pin count flip chip assembly by providing good co-planarity. Coining of solder bumps on PCB has been successfully demonstrated using a modified tension/compression tester with height, coining rate and coining temperature variables. It was observed that applied loads as a function of coined height showed three stages as coining deformation : (1) elastic deformation at early stage, (2) linear increase of applied load, and (3) rapid increase of applied load. In order to reduce applied loads for coining solder bumps on PCB, effects of coining process parameters were investigated. Coining loads for solder bump deformation strongly depended on coining rates and coining temperatures. As coining rates decreased and process temperature increased, coining loads decreased. Among the effect of two factors on coining loads, it was found that process temperature had more significant effect to reduce applied coining loads during the coining process. Lower coining loads were needed to prevent substrate damages such as micro-via failure and build-up dielectric layer thickness change during applying loads. For flip chip assembly, 97Pb/Sn flip chip bumped devices were successfully assembled on organic substrates with 37Pb/Sn coined flip chip bumps.

• Korean Journal of Construction Engineering and Management
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• v.5 no.5 s.21
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• pp.163-171
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• 2004

This research investigates a Modeling Spell Checker that, similarly to Word Spell Checker for word processing software, would conform as-built 3D models to standard construction rules. The work is focused on the study of pipe-spools. Specifically pipe diameters and coplanarity are checked and corrected by the Modeling Spell Checker, and elbows are deduced and modeled to complete models. Experiments have been conducted by scanning scenes of increasing levels of complexity regarding the number of pipes, the types of elbows and the number of planes constituting pipe-spools. For building models of pipes from sensed data, a modeling method, developed at the University of Texas at Austin, that is based on the acquisition of sparse point clouds and the human ability to recognize geometric shapes has been used Results show that primitive-based models obtained after scanning construction sites can be corrected and even improved automatically, and, since such models are expected to be used as feedback control models for equipment operators, the higher modeling accuracy achieved with the Modeling Spell Checker could potentially increase the level of safety in construction. Result also show that some improvements are still needed especially regarding the co-planarity of pipes. In addition, results show that the modeling accuracy significantly depends on the primitive modeling method, and improvement of that method would positively impact the modeling spell checker.

• Proceedings of the KIEE Conference
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• 2006.07c
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• pp.1450-1451
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• 2006

In this paper, we first applied the chemical mechanical polishing (CMP) process to the planarization of ferroelectric film in order to obtain a good planarity of electrode/ferroelectric film interface. $Bi_{3.25}La_{0.75}Ti_{3}O_{12}$ (BLT) ferroelectric fan was fabricated by the sol-gel method. Removal rate and non-uniformity (WIWNU%) were examined by change of silica slurries pH(10.3, 11.3, 12.3). Surface roughness of BLT thin films before and after CMP process was inquired into by atomic force microscopy (AFM). Effects of silica slurries pH(10.3, 11.3, 12.3) were investigated on the CMP performance of BLT film by the surface analysis of X-ray photoelectron spectroscopy(XPS).

• Transactions on Electrical and Electronic Materials
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• v.14 no.2
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• pp.63-66
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• 2013

This paper describes the highly productive process technologies of microprobe arrays, which were used for a probe card to test a Dynamic Random Access Memory (DRAM) chip with fine pitch pads. Cantilever-type microprobe arrays were fabricated using conventional micro-electro-mechanical system (MEMS) process technologies. Bonding material, gold-tin (Au-Sn) paste, was used to bond the Ni-Co alloy microprobes to the ceramic space transformer. The electrical and mechanical characteristics of a probe card with fabricated microprobes were measured by a conventional probe card tester. A probe card assembled with the fabricated microprobes showed good x-y alignment and planarity errors within ${\pm}5{\mu}m$ and ${\pm}10{\mu}m$, respectively. In addition, the average leakage current and contact resistance were approximately 1.04 nA and 0.054 ohm, respectively. The proposed highly productive microprobes can be applied to a MEMS probe card, to test a DRAM chip with fine pitch pads.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2004.07a
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• pp.224-226
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• 2004

CMP process requirements become tighter especially in sub-100nm technology. Especially, high planarity and low defectivity appear as leading issues in CMP technology. Also, the introduction of new materials and advanced lithography technique increases CMP applications. Here are listed some major issues and challenges in CMP technology, which can be categorized following four items. These have practical significance and should be considered more concretely for future generation.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2003.11a
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• pp.140-143
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• 2003

BST thin films have a good thermal-chemical stability, insulating effect and variety of phases. However, BST thin films have problems of the aging effect and mismatch between the BST thin film and electrode. Also, due to the high defect density and surface roughness at grain boundarys and in the grains, which degrades the device performances. In order to overcome these weakness, we first applied the chemical mechanical polishing (CMP) process to the polishing of ferroelectric film in order to obtain a good planarity of electrode/ferroelectric film interface. BST ferroelectric film was fabricated by the sol-gel method. And then, we compared the structural characteristics before and after CMP process of BST films. We expect that our results will be useful promise of global planarization for FRAM application in the near future.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2006.06a
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• pp.55-56
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• 2006

In this paper, we first applied the chemical mechanical polishing (CMP) process to the planarization of ferroelectric film in order to obtain a good planarity of electrode/ferroelectric film interface. BST ($Ba_{0.6}Sr_{0.4}TiO_3$), PZT ($Pb_{1.1}(Zr_{0.52}TiO_{0.48})O_3$) and BTO ($BaTiO_3$) ferroelectric film are fabricated by the sol-gel method. And then, we compared the structural characteristics before and after CMP process of BST, PZT, BTO films. Their dependence on slurry composition was also investigated. We expect that our results will be useful promise of global planarization for ferroelectric random access memories (FRAM) application in the near future.

• Journal of Radiation Industry
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• v.4 no.1
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• pp.1-6
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• 2010

The purpose of this study is to synthesize the radio fluorine labelled isoquinoline salt derivative as new radiopharmaceutical for imaging tumors using positron emission tomography (PET). The planarity of isoquinoline allows to inhibit topoisomerase or intercalate between adjacent DNA base pairs, which result in producing double strand breaks in the DNA and a cell death. Therefore, the isoquinoline has seemed to have a potential anticancer activity. In order to obtain 2-(5-[$^{18}F$]fluoropentylisoquinolinium salt with good radiochemical yield, tosylated precursors have been synthesized. The labelling reaction was carried out for 30 minute in HMPA at $120^{\circ}C$. The radiochemical yield was about 50~60%.

• Journal of the Korean Society of Manufacturing Process Engineers
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• v.18 no.11
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• pp.24-34
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• 2019

An automotive automatic transmission is a popular power-transmitting device in passenger vehicles, as it provides various speed ratios for diverse driving conditions with easy manipulation and smooth gear shifting. The transmission is mainly composed of input and output shafts, planetary gear sets, brakes/clutches, and housing, and it yields multiple forward gears and one reverse gear by actuating the shifting devices of the brakes and clutches. In developing a new transmission, kinematic configurations of a transmission, which presents a brief structure and actuation schemes for speed ratios, need to be checked to determine if the structure can be assembled in a layout. It is impossible for a transmission concept having any interference in connecting main components to be developed further in the design process, since connection interference leads to failure of a layout design in the 2-D plane. In this research, an analysis of the assemblability of a front-wheel drive automatic transmission is carried out on an example concept design by applying the vertex addition algorithm based on graph theory.