• Journal of the Institute of Electronics Engineers of Korea TC
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• v.43 no.2 s.344
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• pp.56-65
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• 2006

In this paper, we introduce modified difference type symbol timing detection method of simple structure and show the relations between S/N ratio and timing detection performance which less influenced by multipath channel delay profile and added noise level and it show very exact GI detection performance characteristics. In the computer simulations, 4 symbol time duration of short and long training of IEEE802.11a standard OFDM frame are used for symbol synchronization timing detection. The computer simulation results show the very exact symbol timing detection performance characteristic within 1 sample error of OFDM signal regardless channel delay profile from minimn phase channels of phase rotation ${\pi}/2$ to non-minimum phase channels of phase rotation ${\pi}/2$ of received OFDM signal and added noise level in channel.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.6 no.4
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• pp.567-573
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• 2002

In this paper, we propose a new symbol time synchronization scheme suitable for the OFDM system with an interpolator. The proposed scheme performs the following three steps. In the first step, the coarse symbol time synchronization is achieved by continuously measuring the average power of the received envelope signal. Based on this average power, the detection possibility for the symbol time synchronization is determined. It the signal is sufficient for synchronization, we next perform a relatively accurate symbol time synchronization by measuring the correlation between a short training signal and the received envelope signal. Finally, an additional frequency synchronization is performed with a long training signal to correct symbol synchronization errors caused by the phase rotation. From the simulation results, one can see that the proposed synchronization scheme provides a good synchronization performance over frequency selective channels.

• Transactions of the Korean Society of Mechanical Engineers B
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• v.24 no.1
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• pp.114-123
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• 2000

The flow structure around a rotating axial-fan was experimentally investigated using a phase averaging velocity field measurement technique. The fan blades were divided into 4 different phases, for which 500 velocity fields were acquired for each phase angle with a 2-frame PTV system. Velocity field measurements were also carried out at two planes parallel to the axis of rotation, with offsets toward the radial direction of the fan. For accurate synchronization of the PTV system with the phase of the axial fan, two synchronization circuits were employed with a photo-detector attached to the rotating shaft. The phase averaged velocity fields show periodic variations with respect to the blade phase. The periodic formation of vortices at the blade tip is also observed in vorticity contour plots. Locations of local maximum turbulence intensities in the axial and radial directions are found to be located in an alternating pattern. These experimental results can be used to validate numerical calculations and to understand the flow characteristics of an axial fan.

• The Transactions of the Korean Institute of Power Electronics
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• v.23 no.4
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• pp.231-239
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• 2018

The phase-locked loop (PLL) is widely used in grid-tie inverter applications to achieve a synchronization between the inverter and the grid. However, its performance deteriorates when the grid voltage is not purely sinusoidal due to the harmonics and the frequency deviation. Therefore, a high-performance PLL must be designed for single-phase inverter applications to guarantee the quality of the inverter output. This paper proposes a simple method that can improve the performance of the PLL for the single-phase inverter under a non-sinusoidal grid voltage condition. The proposed PLL can accurately estimate the fundamental frequency and theta component of the grid voltage even in the presence of harmonic components. In addition, its transient response is fast enough to track a grid voltage within two cycles of the fundamental frequency. The effectiveness of the proposed PLL is confirmed through the PSIM simulation and experiments.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.44 no.5
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• pp.45-53
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• 2007

To recover transmitted signal perfectly at DTV receiver, we have to acquire carrier frequency synchronization to compensate pilot signal which located in wrong position and rotated phase. Also, we need a symbol timing synchronization to compensate sampling timing error. Conventionally, to synchronize symbol timing, we use Gardner's scheme which used in multi-level signal. Gardner's scheme is well known for its sampling the timing error signal from every symbol and it makes easy to detect and keep timing sync in multi-path channel. In this paper, to discuss the problem when the received power level is out of range and we cannot get synchronization information. With this problem, we use 2 step procedures. First, we put a received signal power compensation block before Garder's timing error detector. Second, adaptive loop filter to get a fast synchronization information and averaging loop filter's output value to reduce the amount of jitter after synchronization in PLL(Phased Locked Loop) circuit which is used to get a carrier frequency synchronization and symbol timing synchronization. Using the averaging value, we can estimate offset. Based on offset changing ratio, we can adapt adaptive loop filter to carrier frequency and symbol timing synchronization circuit.

• Proceedings of the KIPE Conference
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• 2014.11a
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• pp.87-88
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• 2014

The paper presents a novel phase locked loop(PLL) control method for robust three-phase thyristor dual converters under sag, notch, and phase loss conditions. This method is applied to three line to line voltages of grid to derive three phase angle errors from three separated single-phase PLLs. They can substitute for abnormal phase to guarantee the synchronization in the various grid fault conditions. The performance of novel PLL with moving average method is verified through simulations.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.38C no.2
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• pp.141-154
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• 2013

The technology of precise time-synchronization between signal receive devices for separation distance operation can be a key point for the technology with TDoA-based system. We propose a new method for the higher accuracy of system's time-synchronization in this paper, which uses OCXO and DPLL with high accuracy to achieve phase synchronization at 1 pps (pulse per second) of signal. And the method receive time value from a GPS satellite. Essentially, the performance of GPS with high accuracy refers to long-term frequency stability for its reliability. As per the characteristic, as the GPS timing signals are synchronized continuously, the accuracy of time-synchronization gets improved proportionally. Therefore, if the time synchronization is accomplished, the accuracy of the synchronization can be up to 0.001 ppb (part per billion). Through the improved accuracy of the time-synchronization, the measurement error of TDOA-based location detection technology is evaluated. Consequently, we verify that TDoA-based location measurement error can be greatly improved via using the improved method for time-synchronization error.

• Journal of the Institute of Convergence Signal Processing
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• v.15 no.4
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• pp.169-175
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• 2014

NG-SDH system is connected with networks throughout optical fibers. Network synchronization controller is a necessary for the data synchronization in each optical transmission system. In this paper, we have design and implementation the network synchronization controller using SOPC(system on a programmable chip) design technic. For this network synchronization controller we use FPGA in Altera. FPGA includes 32bit CPU, DPRAM(dual port ram), digital input/output port, transmitter and receiver framer, phase difference detector. We also confirm that designed network synchronization controller satisfies the ITU-T G.813 timing requirements.

• The Journal of the Korea institute of electronic communication sciences
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• v.7 no.1
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• pp.91-96
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• 2012

Recently, the research of security and its related problems has been received great interested. The research for hper-chaos systems and its synchronization are actively processing as one of method to apply to secure and cryptography communication. In this paper, we propose the synchronization method by coupling coefficient of linear and nonlinear in order to accomplish the synchronization of hyper-chaos system that organized by SC-CNN(State-Controlled Cellular Neural Network). We also verify and confirm the result of synchronization between entire transmitter and receiver, and each subsystem in transmitter and receiver through the phase portrait and difference of time-series by the computer simulation.

• Proceedings of the KIPE Conference
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• 2018.11a
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• pp.104-106
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• 2018

The harmonics and the DC offset in the grid can cause serious synchronization problems for grid connected inverters (GCIs) which leads not able to satisfy the IEEE 519 and p1547 standards in terms of phase and frequency variations. In order to guarantee the smooth and reliable synchronization of GCIs with the grid, Phase Locked Loop (PLL) is the crucial element. Typically, the performance of the PLL is assessed to limit the grid disturbances e.g. grid harmonics, DC Offset and voltage sag etc. To ensure the quality of GCI, the PLL should be precise in estimating the grid amplitude, frequency and phase. Therefore, in this paper a novel Robust PLL technique called Digital Lock-in Amplifier (DLA) PLL is proposed. The proposed PLL estimate the frequency variations and phase errors accurately even in the highly distorted grid voltage conditions like grid voltage harmonics, DC offsets and grid voltage sag. To verify the performance of proposed method, it is compared with other six conventional used PLLs (CCF PLL, SOGI PLL, SOGI LPF PLL, APF PLL, dqDSC PLL, MAF PLL). The comparison is done by simulations on MATLAB Simulink. Finally, the experimental results are verified with Single Phase GCI Prototype.