• Title/Summary/Keyword: phase matching

Search Result 409, Processing Time 0.029 seconds

Unveiling Quenching History of Cluster Galaxies Using Phase-space Analysis

  • Rhee, Jinsu;Smith, Rory;Yi, Sukyoung K.
    • The Bulletin of The Korean Astronomical Society
    • /
    • v.44 no.1
    • /
    • pp.40.1-40.1
    • /
    • 2019
  • We utilize times since infall of cluster galaxies obtained from Yonsei Zoom-in Cluster Simulation (YZiCS), the cosmological hydrodynamic N-body simulations, and star formation rates from the SDSS data release 10 to study how quickly late-type galaxies are quenched in the cluster environments. In particular, we confirm that the distributions of both simulated and observed galaxies in phase-space diagrams are comparable and that each location of phase-space can provide the information of times since infall and star formation rates of cluster galaxies. Then, by limiting the location of phase-space of simulated and observed galaxies, we associate their star formation rates at z ~ 0.08 with times since infall using an abundance matching technique that employs the 10 quantiles of each probability distribution. Using a flexible quenching model covering different quenching scenarios, we find the star formation history of satellite galaxies that best reproduces the obtained relationship between time since infall and star formation rate at z ~ 0.08. Based on the derived star formation history, we constrain the quenching timescale (2 - 7 Gyr) with a clear stellar mass trend and confirm that the refined model is consistent with the "delayed-then-rapid" quenching scenario: the constant delayed phase as ~ 2.3 Gyr and the quenching efficiencies (i.e., e-folding timescale) outside and inside clusters as ~ 2 - 4 Gyr (${\propto}M_*^{-1}$) and 0.5 - 1.5 Gyr (${\propto}M_*^{-2}$), Finally, we suggest: (i) ram-pressure is the main driver of quenching of satellite galaxies for the local Universe, (ii) the quenching trend on stellar mass at z > 0.5 indicates other quenching mechanisms as the main driver.

  • PDF

Developing a Drawing Template for BIM software to Improve BIM-based Drawing Work Efficiency in the Construction Document Phase (실시설계단계 BIM 기반 도면 작업 효율 향상을 위한 도면화 템플릿 개발)

  • Kim, Yi-Je;Kim, In-Chie;Chin, Sang-Yoon
    • Journal of KIBIM
    • /
    • v.10 no.4
    • /
    • pp.98-109
    • /
    • 2020
  • Based on the prior research which developed the consistency review checklist of the BIM model and 2D drawing through the drawing analysis of the construction documents phase, the apparent limits of the existing template and the template development items were derived. As well, the BIM-based drawing templates of the construction documentation phase were developed and verified using ArchiCAD BIM software. The developed template was then applied to the actual project model in the construction documents phase, and, as a result, 50% of existing work elements could be utilized as templates. This is an increase of more than 30% over the existing template utilization elements, and it is analyzed to be effective in practical application and utilization. Based on the results of this study, if the BIM model construction criteria matching the drawing's utilization purpose are presented, while at the same time the BIM data interlocking and drawing template development studies are conducted, the utilization of BIM data can be maximized and additional drawing work can be minimized to increase the percentage of template utilization elements. In addition, it is believed that this can employed to address functional and institutional problems of BIM-based drawing and make a contribution to the activation of BIM.

Implementation of a CMOS FM RX front-end with an automatic tunable input matching network (자동 변환 임피던스 매칭 네트워크를 갖는 CMOS FM 수신기 프론트엔드 구현)

  • Kim, Yeon-Bo;Moon, Hyunwon
    • Journal of Korea Society of Industrial Information Systems
    • /
    • v.19 no.4
    • /
    • pp.17-24
    • /
    • 2014
  • In this paper, we propose a CMOS FM RX front-end structure with an automatic tunable input matching network and implement it using a 65nm CMOS technology. The proposed FM RX front-end is designed to change the resonance frequency of the input matching network at the low noise amplifier (LNA) according to the channel frequency selected by a phase-locked loop (PLL) for maintaining almost constant sensitivity level when an embedded antenna type with high frequency selectivity characteristic is used for FM receiver. The simulation results of implemented FM front-end show about 38dB of voltage gain, below 2.5dB of noise figure, and -15.5dBm of input referred intercept point (IIP3) respectively, while drawing only 3.5mA from 1.8V supply voltage including an LO buffer.

The study of data transfer method non-matching meshes interface using common-refinement method for fluid-structure interface (유체-구조 연성 해석을 위한 common-refinement 기반 불일치 격자 경계면에서의 정보 전달 기법 연구)

  • Han, Sangho;Kim, Donghyun;Lee, Changsoo;Kim, Chongam
    • Journal of the Korean Society for Aeronautical & Space Sciences
    • /
    • v.42 no.3
    • /
    • pp.191-198
    • /
    • 2014
  • During multi-physics or multi-phase simulations accompanying fluid- structure- thermal interaction, data transfer problems always arise along non- matching interfaces caused by different computational meshes for each physical domain. Common- refinement scheme, among many available methods, is attractive since it is known to yield conservative and accurate data transfer for non- matching interface cases. This is particularly important in simulating compressible unsteady fluid- structure- thermal interaction inside solid propellant rockets, where grid size along solid- fluid interfaces is substantially different. From this perspective, we examine performances of common- refinement- based data transfer scheme between structured quadrilateral (structure part) and unstructured triangular (fluid part) meshes by comparing computed results with other data transfer methods.

Dual-Band Class F Power Amplifier using CRLH-TLs for Multi-Band Antenna System (다중밴드 안테나 시스템을 위한 CRLH 전송선로를 이용한 이중대역 Class F 전력증폭기)

  • Kim, Sun-Young;Seo, Chul-Hun
    • Journal of the Institute of Electronics Engineers of Korea TC
    • /
    • v.45 no.12
    • /
    • pp.7-12
    • /
    • 2008
  • In this paper, a highly efficiency power amplifier is presented for multi-band antenna system. The class F power amplifier operating in dual-band designed with one LDMOSFET. An operating frequency of power amplifier is 900 MHz and 2.14 GHz respectively Matching networks and harmonic control circuits of amplifier are designed by using the unit cell of composite right/left-handed(CRLH) transmission line(TL) realized with lumped elements. The CRLH TL can lead to metamaterial transmission line with the dual-band holing capability. The dual-band operation of the CRLH TL is achieved by the frequency offset and the nonlinear phase slope of the CRLH TL for the matching network of the power amplifier. Because the control of all harmonic components for high efficiency is very difficult, we have controled only the second- and third-harmonics to obtain the high efficiency with the CRLH TL. Also, the proposed power amplifier has been realized by using the harmonic control circuit for not only the output matching network, but also the input matching network for better efficiency.

Parallel Approximate String Matching with k-Mismatches for Multiple Fixed-Length Patterns in DNA Sequences on Graphics Processing Units (GPU을 이용한 다중 고정 길이 패턴을 갖는 DNA 시퀀스에 대한 k-Mismatches에 의한 근사적 병열 스트링 매칭)

  • Ho, ThienLuan;Kim, HyunJin;Oh, SeungRohk
    • The Transactions of The Korean Institute of Electrical Engineers
    • /
    • v.66 no.6
    • /
    • pp.955-961
    • /
    • 2017
  • In this paper, we propose a parallel approximate string matching algorithm with k-mismatches for multiple fixed-length patterns (PMASM) in DNA sequences. PMASM is developed from parallel single pattern approximate string matching algorithms to effectively calculate the Hamming distances for multiple patterns with a fixed-length. In the preprocessing phase of PMASM, all target patterns are binary encoded and stored into a look-up memory. With each input character from the input string, the Hamming distances between a substring and all patterns can be updated at the same time based on the binary encoding information in the look-up memory. Moreover, PMASM adopts graphics processing units (GPUs) to process the data computations in parallel. This paper presents three kinds of PMASM implementation methods in GPUs: thread PMASM, block-thread PMASM, and shared-mem PMASM methods. The shared-mem PMASM method gives an example to effectively make use of the GPU parallel capacity. Moreover, it also exploits special features of the CUDA (Compute Unified Device Architecture) memory structure to optimize the performance. In the experiments with DNA sequences, the proposed PMASM on GPU is 385, 77, and 64 times faster than the traditional naive algorithm, the shift-add algorithm and the single thread PMASM implementation on CPU. With the same NVIDIA GPU model, the performance of the proposed approach is enhanced up to 44% and 21%, compared with the naive, and the shift-add algorithms.

Lamb Wave Technique for Ultrasonic Nonlinear Characterization in Elastic Plates (판재의 초음파 비선형 특성평가를 위한 Lamb Wave 기법)

  • Lee, Tae-Hun;Kim, Chung-Seok;Jhang, Kyung-Young
    • Journal of the Korean Society for Nondestructive Testing
    • /
    • v.30 no.5
    • /
    • pp.458-463
    • /
    • 2010
  • Since the acoustic nonlinearity is sensitive to the minute variation of material properties, the nonlinear ultrasonic technique(NUT) has been considered as a promising method to evaluate the material degradation or fatigue. However, there are certain limitations to apply the conventional NUT using the bulk wave to thin plates. In case of plates, the use of Lamb wave can be considered, however, the propagation characteristics of Lamb wave are completely different with the bulk wave, and thus the separate study for the nonlinearity of Lamb wave is required. For this work, this paper analyzed first the conditions of mode pair suitable for the practical application as well as for the cumulative propagation of quadratic harmonic frequency and summarized the result in for conditions; (1) phase matching, (2) non-zero power flux, (3) group velocity matching, and (4) non-zero out-of-plane displacement. Experimental results in aluminum plates showed that the amplitude of the secondary Lamb wave and nonlinear parameter growed up with increasing propagation distance at the mode pair satisfying the above all conditions and that the ration of nonlinear parameters measured in Al6061-T6 and Al1100-H15 was closed to the ratio of the absolute nonlinear parameters.

Design and Implementation of QPSK Receiver Using Six-Port Direct Conversion (Six-Port 직접 변환을 이용한 QPSK 수신기 설계 및 제작)

  • Yang, Woo-Jin;Kim, Young-Wan
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
    • /
    • v.18 no.1 s.116
    • /
    • pp.15-23
    • /
    • 2007
  • A simple six-port direct conversion QPSK receiver which is made up of a six-port phase correlator, a signal power detector, and I/Q channel signal de-modulator is designed and implemented in this paper. The output phase signals of six-port phase correlator are also analysed. On the basis of $90^{\circ}C$ phase relation among the six-port phase correlator output signals, the QPSK de-modulation circuit is designed by a simple circuit. The six-port phase correlator is made up of $90^{\circ}$ hybrid branch line and power detector. The six-port phase correlator, which is designed in frequency range of 11.7 to 12.0 GHz, gets the phase error characteristics less than $5^{\circ}$. By considering matching network and amplitude balance in the designed fiequency range, the designed six-port direct conversion QPSK receiver demodulates the I and Q signals with performance less than $5^{\circ}$ phase error.

Location Error Analysis of an Active RFID-Based RTLS in Multipath and AWGN Environments

  • Myong, Seung-Il;Mo, Sang-Hyun;Yang, Hoe-Sung;Cha, Jong-Sub;Lee, Heyung-Sub;Seo, Dong-Sun
    • ETRI Journal
    • /
    • v.33 no.4
    • /
    • pp.528-536
    • /
    • 2011
  • In this paper, we analyze the location accuracy of real-time locating systems (RTLSs) in multipath environments in which the RTLSs comply with the ISO/IEC 24730-2 international standard. To analyze the location error of RTLS in multipath environments, we consider a direct path and indirect path, in which time and phase are delayed, and also white Gaussian noise is added. The location error depends strongly on both the noise level and phase difference under a low signal-to-noise ratio (SNR) regime, but only on the noise level under a high SNR regime. The phase difference effect can be minimized by matching it to the time delay difference at a ratio of 180 degrees per 1 chip time delay (Tc). At a relatively high SNR of 10 dB, a location error of less than 3 m is expected at any phase and time delay value of an indirect signal. At a low SNR regime, the location error range increases to 8.1 m at a 0.5 Tc, and to 7.3 m at a 1.5 Tc. However, if the correlation energy is accumulated for an 8-bit period, the location error can be reduced to 3.9 m and 2.5 m, respectively.

An In-Band Noise Filtering 32-tap FIR-Embedded ΔΣ Digital Fractional-N PLL

  • Lee, Jong Mi;Jee, Dong-Woo;Kim, Byungsub;Park, Hong-June;Sim, Jae-Yoon
    • JSTS:Journal of Semiconductor Technology and Science
    • /
    • v.15 no.3
    • /
    • pp.342-348
    • /
    • 2015
  • This paper presents a 1.9-GHz digital ${{\Delta}{\Sigma}}$ fractional-N PLL with a finite impulse response (FIR) filter embedded for noise suppression. The proposed digital implementation of FIR provides a simple method of increasing the number of taps without complicated calculation for gain matching. This work demonstrates 32 tap FIR filtering for the first time and successfully filtered the in-band phase noise generated from delta-sigma modulator (DSM). Design considerations are also addressed to find the optimum number of taps when the resolution of time-to-digital converter (TDC) is given. The PLL, fabricated in $0.11-{\mu}m$ CMOS, achieves a well-regulated in-band phase noise of less than -100 dBc/Hz for the entire range inside the bandwidth of 3 MHz. Compared with the conventional dual-modulus division, the proposed PLL shows an overall noise suppression of about 15dB both at in-band and out-of-band region.