• 대한전기학회:학술대회논문집
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• 대한전기학회 2000년도 추계학술대회 논문집 학회본부 B
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• pp.381-383
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• 2000

The photovoltaic power generation system has a great future as clean energy instead of fossil fuel which has many environmental problems such as exhausted gas or air pollution. In a utility interactive photovoltaic generation system, a three-phase inverter is used for the connection between the photovoltaic array and the utility. This paper presents a three phase inverter for photovoltaic power system with current controller, voltage controller, PLL control system and the phase detector of interactive voltage by using da transformation. The proposed inverter system provides a sinusoidal ac current for domestic loads and the utility line with unity power factor. The results of the operated from January to October show the system characteristics.

• Journal of Power Electronics
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• 제18권5호
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• pp.1523-1535
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• 2018

High-performance Phase-Locked Loops (PLLs) are critical for grid synchronization in grid-tied power electronic applications. In this paper, a new single-phase All Digital Phase-Locked Loop (ADPLL) is proposed. It features fast transient response and good robustness under distorted grid conditions. It is designed for Field Programmable Gate Array (FPGA) implementation. As a result, a high sampling frequency of 1MHz can be obtained. In addition, a new OSG is adopted to track the power frequency, improve the harmonic rejection and remove the dc offset. Unlike previous methods, it avoids extra feedback loop, which results in an enlarged system bandwidth, enhanced stability and improved dynamic performance. In this case, a new parameter optimization method with consideration of loop delay is employed to achieve a fast dynamic response and guarantee accuracy. The Phase Detector (PD) and Voltage Controlled Oscillator (VCO) are realized by a Coordinate Rotation Digital Computer (CORDIC) algorithm and a Direct Digital Synthesis (DDS) block, respectively. The whole PLL system is finally produced on a FPGA. A theoretical analysis and experiments under various distorted grid conditions, including voltage sag, phase jump, frequency step, harmonics distortion, dc offset and combined disturbances, are also presented to verify the fast dynamic response and good robustness of the ADPLL.

• 한국전자파학회논문지
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• 제10권6호
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• pp.816-824
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• 1999

본 논문에서는 아날로그 위상비교기률 이용한 위상고정루프를 소개하였으며. 이 방법을 이용하여 20 GHz 대 고정국용 위상고정 국부발진기를 설계 제작하였다. 이 국부발진기는 하이브리드 형태의 18 GHz VCDRO (Voltage Controlled Dielectric Resonator Oscillator)와 완충증폭기 및 아날로그 위상검출기로 이루어져 있다. 일반적인 크리스탈 발전기의 N배 이외의 주파수를 위상고정하기 위하여 VHF PLL로 구성되어 있다. 국부발 진기의 발진전력은 18 GHz에서 약 21 dBm. 고조파억압은 - 34 dBc로 안정된 위상고정 상태를 나타내었다. 이때의 SSB위상잡음은 -75 dBc/Hz@10 kHz로 측정되었다.

• 대한전자공학회논문지TC
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• 제38권4호
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• pp.11-17
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• 2001

본 논문에서는 High-Order QAM(Quandrature Amplitude Modulation)을 적용하는 모뎀에서 강인하고 넓은 범위의 주파수 포착 범위를 가지는 극성판단(Polarity Decision) 반송파 동기용 PD(Phase Detector) 알고리즘을 제안하고 이에 대한 평균 출력특성(S-curve)과 분산특성을 수학적으로 유도하여 기존의 DD(Decision Directed)방식과 비교 분석한다. 기존의 DD 방식의 선형영역은 256 QAM의 경우 $3.5^{\circ}{\sim}3.5^{\circ}$ 이었으나 제안한 알고리즘의 선형영역은 ${\gamma}-17.9$에서 $36^{\circ}{\sim}36^{\circ}$ 의 넓은 구간을 가진다. 또한 기존의 DD 방식에서는 256 QAM의 주파수 오프셋 포착 성능이 ${\pm}10\;KHz$ 이하였다. 이는 아날로그 front-end 회로에서 주파수 오프셋이 일반적으로 ${\pm}100\;KHz$ 정도까지 줄어들 수 잇는 것을 감안하면 AFC(Automatic Frequency Control) 또는 반송파 복구를 위한 보조적인 위상검출회로가 필요하게 됨을 의미한다. 그러나 제안된 극성판단 반송파 동기 알고리즘을 사용하면 보조적인 회로의 도움없이 SNR = 30 dB에서 최대 ${\pm}300\;KHz$의 주파수 오프셋까지도 포착 가능하다.

• Journal of Astronomy and Space Sciences
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• 제30권3호
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• pp.175-178
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• 2013

Recently, two instruments of cosmic ray are operating in South Korea. One is Seoul muon detector after October 1999 and the other is Daejeon neutron monitor (Kang et al. 2012) after October 2011. The former consists of four small plastic scintillators and the latter is the standard 18 NM 64 type. In this report, we introduce the characteristics of both instruments. We also analyze the flux variations of cosmic ray such as diurnal variation and Forbush decrease. As the result, the muon flux shows the typical seasonal and diurnal variations. The neutron flux also shows the diurnal variation. The phase which shows the maximum flux in the diurnal variation is around 13-14 local time. We found a Forbush decrease on 7 March 2012 by both instruments. It is also identified by Nagoya multi-direction muon telescope and Oulu neutron monitor. The observation of cosmic ray at Jangbogo station as well as in Korean peninsula can support the important information on space weather in local area. It can also enhance the status of Korea in the international community of cosmic ray experiments.

• Journal of the Korean Wood Science and Technology
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• 제45권4호
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• pp.471-481
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• 2017

As the molecular weight (MW) of urea-formaldehyde (UF) resins had a great impact on their properties, this work was conducted to study effect of analytical parameters of gel permeation chromatography (GPC) on the MW measurement of UF resins. GPC parameters such as flow rate, column, detector temperature, and sample injection temperature were selected to compare number-average molecular weight (Mn), weight-average molecular weight (Mw), molecular weight distribution (MWD) and polydispersity index (PDI) of two UF resins with different viscosities. As expected, UF resin with higher viscosity resulted in greater Mn and Mw than those of low viscosity UF resin. When the flow rate increased, both Mn and Mw of UF resins decreased and MWD became narrower. By contrast, both Mn and Mw increased and MWD became wide when the column, detector, and sample injection temperature increased. The column, detector, and sample injection temperature of $50^{\circ}C$ at a flow rate of $0.5m{\ell}/min$ resulted in the highest MW and broadest MWD for the GPC analysis. These results suggest that the apparent molecular size or a hydrodynamic radius of UF resin molecules dissolved in the mobile phase affect to Mn, Mw and MWD.

• 한국인터넷방송통신학회논문지
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• 제13권6호
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• pp.109-114
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• 2013

낮은 저항이나 좋은 전기투과도 지점으로 알려진 생물학적 활성점(biological active points, BAP)인 BAP검출을 위한 새로운 방법으로 적응주파수추적필터와 과도이벤트검출을 기반으로 하는 생체임피던스측정시스템을 사용하는 방식에 대해 제안하였다. 이 생체임피던스장치에 다중주파수 전류주입과 전압측정 모두 표면전극을 사용하였다. 또한 마이크로컨트롤러를 통하여 적응주파수추적필터를 사용한 다중주파수요소에 의해 변조된 신호의 연속적인 복조를 처리하였다. 또한 위상공간방식의 과도이벤트검출방식이 제안된 BAP등가모델에 각주파수에 대해 적용되었다.

• KSII Transactions on Internet and Information Systems (TIIS)
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• 제11권11호
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• pp.5574-5591
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• 2017

Inspired by the idea of Artificial Immune System, many researches of wireless sensor network (WSN) intrusion detection is based on the artificial intelligent system (AIS). However, a large number of generated detectors, black hole, overlap problem of NSA have impeded further used in WSN. In order to improve the anomaly detection performance for WSN, detector generation mechanism need to be improved. Therefore, in this paper, a Differential Evolution Constraint Multi-objective Optimization Problem based Negative Selection Algorithm (DE-CMOP based NSA) is proposed to optimize the distribution and effectiveness of the detector. By combining the constraint handling and multi-objective optimization technique, the algorithm is able to generate the detector set with maximized coverage of non-self space and minimized overlap among detectors. By employing differential evolution, the algorithm can reduce the black hole effectively. The experiment results show that our proposed scheme provides improved NSA algorithm in-terms, the detectors generated by the DE-CMOP based NSA more uniform with less overlap and minimum black hole, thus effectively improves the intrusion detection performance. At the same time, the new algorithm reduces the number of detectors which reduces the complexity of detection phase. Thus, this makes it suitable for intrusion detection in WSN.

• 센서학회지
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• 제16권6호
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• pp.475-483
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• 2007

This paper proposes a readout integrated circuit (ROIC) for $32{\times}32$ infrared focal plane array (IRFPA) detector, which consist of reference resistor, detector resistor, reset switch, integrated capacitor and operational amplifier. Proposed ROIC is designed using $0.35{\;}{\mu}m$ 2P-4M (double poly four metal) n-well CMOS process parameters. Low noise folded cascode operational amplifier which is a key element in the ROIC showed 12.8 MHz unity-gain bandwidth and open-gain 89 dB, phase margin $67^{\circ}$, SNR 82 dB. From proposed circuit, we gained output voltage variation ${\Delta}17{\};mV/^{\circ}C$ when the detector resistor varied according to the temperature.

• JSTS:Journal of Semiconductor Technology and Science
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• 제11권2호
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• pp.73-79
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• 2011

This paper describes a reset-free delay-locked loop (DLL) for a memory controller application, with the aid of a hysteresis coarse lock detector. The coarse lock loop in the proposed DLL adjusts the delay between input and output clock within the pull-in range of the main loop phase detector. In addition, it monitors the main loop's lock status by dividing the input clock and counting its multiphase edges. Moreover, by using hysteresis, it controls the coarse lock range, thus reduces jitter. The proposed DLL neither suffers from harmonic lock and stuck problems nor needs an external reset or start-up signal. In a 0.13-${\mu}m$ CMOS process, post-layout simulation demonstrates that, even with a switching supply noise, the peak-to-peak jitter is less than 30 ps over the operating range of 500-1200 MHz. It occupies 0.04 $mm^2$ and dissipates 16.6 mW at 1.2 GHz.