• Journal of the Institute of Electronics Engineers of Korea TC
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• v.38 no.4
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• pp.11-17
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• 2001

In this paper, we propose a polarity decision carrier recovery algorithm for high order QAM(Quadrature Amplitude Modulation), which has robust and large frequency acquisition performance in the high order QAM modem. The proposed polarity decision PD(Phase Detector) output and its variance characteristic are mathematically derived and the simulation results are compared with conventional DD(Decision-Directed) method. While the conventional DD algorithm has linear range of $3.5^{\circ}{\sim}3.5^{\circ}$, the proposed polarity decision PD algorithm has linear range as large as $-36^{\circ}{\sim}36^{\circ}$ at ${\gamma}-17.9$. The conventional DD algorithm can only acquire offsets less than ${\pm}10\;KHz$ in the case of the 256 QAM while an analog front-end circuit generally can reduce the carrier-frequency offset down to only ${\pm}100\;KHz$. Thus, in this case additional AFC or phase detection circuit for carrier recovery is required. But by adopting the proposed polarity decision algorithm, we can find the system can acquire up to ${\pm}300\;KHz$at SNR = 30dB without aided circuit.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1999.05a
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• pp.234-238
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• 1999

The correlation between shape of electrical trees and partial discharge(PD) pulses in low density polyethylene(LDPE) were discussed. We observed growth feature of electrical tree by using optical microscope. On the basis of experimental results of measurements of trees occurring in the needle-plane arrangement with needle shape void and without needle shape void , statistical quantities are derived, which are relevant to PD pulse amplitude and phase. The PD quantities detected by partial discharge detector. we were analyzed q-n distribution pattern and $\psi$ -q-n distribution pattern. In this experiment, electrical trees in the needle-plane arrangement with needle shape void propagated branch type tree and in the needle-plane arrangement without needle shape void propagated bush type tree

• The Journal of the Korea institute of electronic communication sciences
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• v.14 no.2
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• pp.309-316
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• 2019

In this paper, a low-jitter delay-locked loop that compensates for local clock skew is presented. The proposed DLL consists of a phase splitter, a phase detector(PD), a charge pump, a bias generator, a voltage-controlled delay line(VCDL), and a level converter. The VCDL uses self-biased delay cells using current mode logic(CML) to have insensitive characteristics to temperature and supply noises. The phase splitter generates two reference clocks which are used as the differential inputs of the VCDL. The PD uses the only single clock from the phase splitter because the PD in the proposed circuit uses CMOS logic that consumes less power compared to CML. Therefore, the output of the VCDL is also converted to the rail-to-rail signal by the level converter for the PD as well as the local clock distribution circuit. The proposed circuit has been designed with a $0.13-{\mu}m$ CMOS process. A global CLK with a frequency of 1-GHz is externally applied to the circuit. As a result, after about 19 cycles, the proposed DLL is locked at a point that the control voltage is 597.83mV with the jitter of 1.05ps.

• Proceedings of the KIEE Conference
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• 2004.07c
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• pp.1936-1938
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• 2004

In this paper, we discussed measurement method of PD (Partial Discharge) of 22.9[kV] cable. Cable rail track laying portable detector that can detect partial discharge of cable connection ashes by on-line done spot way to detect Lemke equipment and high broadcasting CT sensor that use antenna sensor using ICM mounting was explained. Because measurement corona signal is very big, analysis of partial discharge is difficult state, we used connector. It could be attenuated by 2 times. We found out that corona signal which generated on B phase is flowed on A phase and C phase. It could measure that partial discharge of A phase happens actually. We could confirm that partial discharge of about 250 ${\sim}$ 300 [pC] on A phase is dangerous.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.38 no.4
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• pp.18-26
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• 2001

In this paper, we propose an ATC(Automatic Transfer mode Controller) algorithm and an average-mode-change method for use in Gear shift PLL which can automatically change loop gain. The proposed ATC algorithm accurately detects proper timing or the mode change and has a very simpler structure - than the conventional lock detector algorithm often used in QPSK. And the proposed average mode change method can obtain low errors of estimated frequency offset by averaging the loop filter output of frequency component in shift register. These algorithms are also useful in designing ASIC, since these algorithms occupy small circuit area and are adaptable for high speed digital processing. We also present phase tracking performance of proposed Gear-shift PLL, which is composed of polarity decision PD, ATC and average mode change circuit, and analyze the results by examining constellation at each mode.

• Journal of Power Electronics
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• v.18 no.5
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• pp.1523-1535
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• 2018

High-performance Phase-Locked Loops (PLLs) are critical for grid synchronization in grid-tied power electronic applications. In this paper, a new single-phase All Digital Phase-Locked Loop (ADPLL) is proposed. It features fast transient response and good robustness under distorted grid conditions. It is designed for Field Programmable Gate Array (FPGA) implementation. As a result, a high sampling frequency of 1MHz can be obtained. In addition, a new OSG is adopted to track the power frequency, improve the harmonic rejection and remove the dc offset. Unlike previous methods, it avoids extra feedback loop, which results in an enlarged system bandwidth, enhanced stability and improved dynamic performance. In this case, a new parameter optimization method with consideration of loop delay is employed to achieve a fast dynamic response and guarantee accuracy. The Phase Detector (PD) and Voltage Controlled Oscillator (VCO) are realized by a Coordinate Rotation Digital Computer (CORDIC) algorithm and a Direct Digital Synthesis (DDS) block, respectively. The whole PLL system is finally produced on a FPGA. A theoretical analysis and experiments under various distorted grid conditions, including voltage sag, phase jump, frequency step, harmonics distortion, dc offset and combined disturbances, are also presented to verify the fast dynamic response and good robustness of the ADPLL.

• Journal of Korean Society of Occupational and Environmental Hygiene
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• v.16 no.3
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• pp.222-232
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• 2006

Objectives: The objective of this study was to propose the total isocyanate analytical method which involves derivation of 2,4-toluene diisocyanate(2,4-TDI), 2,6-toluene diisocyanate(2,6-TDI), 4,4'-methylenediphenyl diisocyanate(4,4'-MDI) and 1,6-hexamethylene diisocyanate(1,6-HDI) using 2-chlorobenzyl alcohol(2-CBA) or 2,4-dichlorobenzyl alcohol(2,4-DCBA), and analyzing of hydrolysate of the synthesized urethane with the gas chromatography(GC)/flame ionization detector(FID), GC/pulsed discharge ionization detector-electron capture detector(PD-ECD) and GC/mass selective detector(MSD). Methods: Urethanes were synthesized by reacting 2,4-TDI, 2,6-TDI, 4,4'-MDI and 1,6-HDI to 2-CBA or 2,4-DCBA. Urethanes was verified by TLC, HPLC/UVD and GC/MSD. For field application, the most suitable condition that 2-CBA coated in glass fiber filter removed completely and urethanes were not removed was searched. 2-CBA generated from hydrolysis of urethanes according to hydrolysis conditions. Diisocyanates were collected on field air and analyzed. Results: Urethanes which were white and solid phase synthesized by reacting 2,4-TDI, 2,6-TDI, 4,4'-MDI, 1,6-HDI and 2-CBA or 2,4-DCBA. And urethanes were verified by TLC, HPLC/UVD and GC/MSD. The most suitable conditions to remove 2-CBA coated in glass fiber filter were $87^{\circ}C$ and 20 mmHg and urethanes were not removed under same condition. Hydrolysis yields of urethanes were 99 % to 111 %. 2-CBA, the hydrolysate of urethanes was analyzed by GC/FID, GC/PD-ECD and GC/MSD. Conclusions: Simultaneous analysis of 2,4-TDI, 2,6-TDI, 4,4'-MDI and 1,6-HDI deriving with 2-CBA and 2,4-DCBA, along with a total isocyanate analysis, was feasible with GC/FID, GC/PD-ECD and GC/MSD. This result will be a guide of further study on total isocyanate analysis.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.4
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• pp.36-42
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• 2008

40Gb/s CMOS Clock and Data Recovery circuit design for optical serial link is proposed. The circuit generates 8 multiphase clock using LC tank PLL and controls the phase between the clock and the data using the $2{\times}$ oversampling Bang-Bang PD. 40Gb/s input data is 1:4 demultiplexed and recovered to 4 channel 10Gb/s outputs. The design was progressed to separate the analog power and the digital power. The area of the chip is $2.8{\times}2.4mm^2$ for the inductors and the power dissipation is about 200mW. The chip has been fabricated using 0.18um CMOS process. The measured results show that the chip recovers the data up to 9.5Gb/s per channel(Equivalent to serial input rate of up to 38Gb/s).

• Archives of Pharmacal Research
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• v.28 no.10
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• pp.1190-1195
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• 2005

The objective of this study was to develop an assay for mequitazine (MQZ) for the study of the bioavailability of the drug in human subjects. Using one mL of human plasma, the pH of the sample was adjusted and MQZ in the aqueous phase extracted with hexane; the organic layer was then evaporated to dryness, reconstituted and an aliquot introduced to a gas chromatograph/mass spectrometer (GC/MS) system with ion-trap detector. Inter- and intra-day precision of the assay were less than 15.1 and $17.7{\%}$, respectively; Inter- and intra-day accuracy were less than 8.91 and $18.6{\%}$, respectively. The limit of quantification for the current assay was set at 1 ng/mL. To determine whether the current assay is applicable in a pharmacokinetic study for MQZ in human, oral formulation containing 10 mg MQZ was administered to healthy male subjects and blood samples collected. The current assay was able to quantify MQZ levels in most of the samples. The maximum concentration ($C_{max}$ was 8.5 ng/mL, which was obtained at 10.1 h, with mean half-life of approximately 45.5 h. Under the current sampling protocol, the ratio of $AUC_{t{\rightarrow}last}$ to $AUC_{t{\rightarrow}{\infty}}$ was $934{\%}$, indicating that the blood collection time of 216 h is reasonable for MQZ. Therefore, these observations indicate that an assay for MQZ in human plasma is developed by using GC/MS with ion-trap detector and validated for the study of pharmacokinetics of single oral dose of 10 mg MQZ, and that the current study design for the bioavailability study is adequate for the drug.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.2
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• pp.19-24
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• 2007

With recent advancement of high-speed, multi-gigabit data transmission capabilities, serial links have been more widely adopted in industry than parallel links. Since the parallel link design forces its transmitter to transmit both the data and the clock to the receiver at the same time, it leads to hardware's intricacy during high-speed data transmission, large power consumption, and high cost. Meanwhile, the serial links allows the transmitter to transmit data only with no synchronized clock information. For the purpose, clock and data recovery circuit becomes a very crucial key block. In this paper, a 5.4Gbps half-rate bang-bang CDR is designed for the applications of high-speed graphic DRAM interface. The CDR consists of a half-rate bang-bang phase detector, a current-mirror charge-pump, a 2nd-order loop filter, and a 4-stage differential ring-type VCO. The PD automatically retimes and demultiplexes the data, generating two 2.7Gb/s sequences. The proposed circuit is realized in 66㎚ CMOS process. With input pseudo-random bit sequences (PRBS) of $2^{13}-1$, the post-layout simulations show 10psRMS clock jitter and $40ps_{p-p}$ retimed data jitter characteristics, and also the power dissipation of 80mW from a single 1.8V supply.