• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2012.05a
• /
• pp.95-98
• /
• 2012

This paper describes a multiphase delay-locked loop (DLL) that generates a 32-phase output clock over the operating frequency range of 40 MHz to 280 MHz. The matrix-based delay line is used for high resolution of 1-bit delay. A calibration scheme, which improves the linearity of a delay line, is achieved by calibrating the nonlinearity of the input stage of the matrix. The multi-phase DLL is fabricated by using 0.11-${\mu}m$ CMOS process with a 1.2 V supply. At the operating frequency of 125MHz, the measurement results shows that the DNL is less than +0.51/-0.12 LSB, and the measured peak-to-peak jitter of the multi-phase DLL is 30 ps with input peak-to-peak jitter of 12.9 ps. The area and power consumption of the implemented DLL are $480{\times}550{\mu}m^2$ and 9.6 mW at the supply voltage of 1.2 V, respectively.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2004.05a
• /
• pp.28-31
• /
• 2004

A Quadrature phase detector for high-speed delay-locked loop is introduced. The proposed Quadrature phase detector is composed of two nor gates and it determines if the phase difference of two input clocks is 90 degrees or not. The delay locked loop circuit including the Quadrature phase detector is fabricated in a 0.18 urn standard CMOS process and it operates at 5 ㎓ frequency. The phase error of the delay-locked loop is maximum 2 degrees and the circuits are robust with voltage, temperature variations.

• Journal of electromagnetic engineering and science
• /
• v.3 no.1
• /
• pp.62-66
• /
• 2003

Novel coupled line phase shifters and its equivalent phase delay line for compact broadband phased array antennas are proposed. These phase control circuits are designed to be less complex, small size and to use a less number of active devices. The phase shifter is able to control a 120$^{\circ}$ phase shift continuously, and the phase delay line for a reference phase has a fixed 60$^{\circ}$ shifted phase. Both have the low phase error of less than $\pm$3.5$^{\circ}$ and the low gain variations of less than 1 ㏈ within the 300 MHz bandwidth. These proposed circuits are adequate to form the efficient beam-forming networks with compactness, broadband, less complexity, and low cost.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.9 no.4
• /
• pp.861-864
• /
• 2005

In this paper, we system the system design and numerical analysis of the ultrafast optical delay line using by optical phase modulator. The numerical analysis carried out with 1310nm, lops laser and electro-optic phase modulator. As the results of numerical analysis, we show a scanning rate of 0.5 GHz and a delay range of 19.0ps. Compare with mechanical delay line, the optical delay line has a high scanning speed and a high repetition rate.

• Journal of the Korea Institute of Military Science and Technology
• /
• v.20 no.3
• /
• pp.413-420
• /
• 2017

We investigate the performance of a true time delay(TTD) phase shifter to reduce the beam squint caused by frequency changes of a phased array antenna in wideband communication systems. To design a high gain phased array antenna, we need a long TTD, which causes high RF loss, low resolution and large dimension of TTD phase shifters. To overcome the problems, we propose a schematic of dual TTD phase shifters, which consists of short time delay(STD) in radio frequency(RF) part and long time delay(LTD) in intermediate frequency(IF) part. Our analysis results show that the proposed scheme reduces the required bits and delay time in RF band of the TTD compared to the conventional single TTD scheme.

• Proceedings of the KIEE Conference
• /
• 1999.07g
• /
• pp.3184-3186
• /
• 1999

In this paper, a new structure of fully differential delay cell VCO using quadrature phase for low phase noise and high speed operation is suggested. It is realized by inserting voltage clamp circuit into input pairs of delay cells that include three-control current source having high output impedance. In this reason. this newly designed delay cell for VCO has the low power supply sensitivity so that the phase noise can be reduced. The whole characteristics of VCO were simulated by using HSPICE and SABER. Simulation results show that the phase noise of new VCO is quite small compared with conventional fully differential delay cell VCO and ring oscillator type VCO. It is also very beneficial to low power supply design because of wide tuning range.

• Proceedings of the KIPE Conference
• /
• 2011.11a
• /
• pp.63-64
• /
• 2011

The inevitable calculation time delay of digital controller especially degrades the voltage control performance of three-phase UPS systems. This paper proposes time delay compensators based on the Smith-predictor for both voltage and current controllers of three-level NPC inverters. The PSIM-based simulation results show that the proposed controller with delay compensator gives improved voltage control performance with respect to time delay.

• The Transactions of The Korean Institute of Electrical Engineers
• /
• v.58 no.1
• /
• pp.187-192
• /
• 2009

This paper presents a method for designing a robust controller that alleviates disturbance effects and compensates performance degradation owing to the time-delay. Disturbance observer(DOB) approach as a tool of robust control has been widely employed in industry. However, since the Pade approximation of time-delay makes the plant non-minimum phase, the classical DOB cannot be applied directly to the system with time-delay. By using a new DOB structure for non-minimum phase systems together with the Smith Predictor, we propose a new controller for reducing the both effects of disturbance and time-delay. Moreover, the closed-loop system can be made robust against uncertain time-delay with the help of a Pill controller tuning method that is based on a second-order plus dead time modeling technique.

• Current Optics and Photonics
• /
• v.8 no.1
• /
• pp.56-64
• /
• 2024

In response to the current situation where general methods cannot effectively compensate for the phase delay of ordinary optical mixers, a multi-layer spatial beam-splitting optical mixer is designed using total reflection triangular prisms and polarization beam splittings. The phase delay is generated by the wave plate, and the mixer can use the existing parallel plates in the structure to individually compensate for the phase of the four output beams. A mixer model is established based on the structure, and the influence of the position and orientation of the optical components on the phase delay is analyzed. The feasibility of the phase compensation method is simulated and analyzed. The results show that the mixer can effectively compensate for the four outputs of the optical mixer over a wide range. The mixer has a compact structure, good performance, and significant advantages in phase error control, production, and tuning, making it suitable for free-space coherent optical communication systems.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.47 no.6
• /
• pp.51-56
• /
• 2010

In this paper, a novel Integer-N phase-delay locked loop(P DLL) architecture has been proposed using a voltage controlled delay line(VCDL). The P DLL can have the LF of one small capacitance instead of the conventional second or third-order LF. The size of chip is $255{\mu}m$ $\times$ $935.5{\mu}m$ including the LF. The proposed P DLL has been designed based on a 1.8V $0.18{\mu}m$ CMOS process and proved by HSPICE simulation.