• JSTS:Journal of Semiconductor Technology and Science
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• v.13 no.6
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• pp.546-550
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• 2013

We propose a novel negative differential resistance (NDR) device with ultra-high peak-to-valley current ratio (PVCR) by combining pn junction diode with depletion mode nanowire (NW) transistor, which suppress the valley current with transistor off-leakage level. Band-to-band tunneling (BTBT) Esaki diode with degenerately doped pn junction can provide multiple switching behavior having multi-peak and valley currents. These multiple NDR characteristics can be controlled by doping concentration of tunnel diode and threshold voltage of NW transistor. By designing our NDR device, PVCR can be over $10^4$ at low operation voltage of 0.5 V in a single peak and valley current.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.32A no.7
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• pp.51-57
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• 1995

The theoretical analysis for AlInAs/GaInAs resonant tunneling diodes (RTDs), which have shown the improved negative differential resistance (NDR) characteristics, has scarcely been made in comparison with AlGaAS/GaAs RTDs. In this paper, the static current-voltage relation of Al$_{0.48}In_{0.52}As/Ga_{0.47}In_{0.53}$As RTDs were numerically estimated by using a self-consistent method. Assuming a simplified RTD with single quantum well structure and spacer layers, the peak current density (J$_{P}$) and the peak-to-valley current ratio (PVCR) were analysed as the function of the thickness of the well, the barrier and the spacer layer, and temperature. As the results, the peak current density and the peak-to-valley current ratio indicated a reciprocal relation roughly in respect to the thicknesses of the well and the barrier, and it was theoretically predicted that it be not attainable to provide a high peak current desity (J$_{P}$) over 1${\times}10^{5}A/cm^{2}$ as well as the large peak-to-valley current ratio (PVCR) over 10 that were the the critical conditions for the practical use.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.18 no.7
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• pp.1036-1043
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• 1993

GaAs/AIGaAs resonant tunneling structures have been grown by atmospheric pressure MOCVD. Resonant tunneling diodes fabricated with the structure grown at 650t showed a high peak-to-valley (P/V) current ratio of 2.35 at room temperature. P/V current ratio increased to 15.3 at 77K. Numerically calculated peak current agrees well with the experimental result. Resonant tunneling diodes with AIGaAs as a barrier and InGaAs as a quantum well and a spacer layer yielded a high P/V current ratio of 4.0 and a peak current density of 8.6KA/c# at room temperature because of increased carrier supply.

• Journal of the Korean Vacuum Society
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• v.1 no.1
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• pp.134-138
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• 1992

The GaAs/AlAs double barrier structures was grown by MBE(Mo1ecular Beam Epitaxy). Mesa diode was fabricated and I-V characteristics of the diode were measured by semiconductor parameter analyser at room temperature. TEM pictures show the double barrier structure with abrupt interface. PVCR(Peak to Valley Current Ratio) proves to be independent of barrier thickness. These results show that increase in barrier thickness leads to larger valley current by non-resonant tunneling.

• The Transactions of the Korean Institute of Power Electronics
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• v.23 no.1
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• pp.59-65
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• 2018

A new single-stage flyback power converter with PFC for electrolytic capacitor-less LED driver is proposed in this study. This method minimizes the peak-to-average ratio of the LED driving pulsating current by adding the LED driving current near the LED current valley area, as well as the third harmonic component injection into the input current. The reduced peak current value of the LED drive current minimizes the thermal stress of the LED itself, thereby increasing the reliability of the LED, as well as achieving a long lifetime. Simulation and experimental results show the usefulness of the proposed topology.

• Proceedings of the KIEE Conference
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• 1996.07c
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• pp.1456-1458
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• 1996

In resonant tunneling diodes with the quantum well structure showing the negative differential resistance (NDR), it is essential to increase both the peak-to-valley current ratio (PVCR) and the peak current density ($J_p$) for the accurate switching operation and the high output of the device. In this work, a resonant interband tunneling diode (RITD) with single quantum well structure, which is composed of $In_{0.53}Ga_{0.47}As/ln_{0.52}Al_{0.48}As$ heterojunction on the InP substrate, is suggested to improve the PVCR and $J_p$ through the narrowed tunnel barriers. As the result, the measured I-V curves showed the PVCR over 60.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.34D no.4
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• pp.27-32
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• 1997

In resonant tunneling diodes with the quantum well structure showing the negative differential resistance (NDR), it is essential to increase both the peak-to-valley current ratio (PVCR) and the peak current desnity ( $J_{p}$) for the accurate digital switching operation and the high output of the device. In this work, a resonant interband tunneling diode (RITD) with single quantum well structure, which is composed of I $n_{0.47}$As/I $n_{0.52}$A $l_{0.48}$As heterojunction on the InP substrate, is fabricated ot improve PVCR and JP, and then the dependence of I-V charcteristics on the width of the quantum well was investigated.d.ted.d.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.31A no.2
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• pp.75-80
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• 1994

AlAs/GaAs/AlAs RTDs(Resonant Tunneling Diodes) are fabricated and current-voltage properties of them are measured. At room temperature, peak to valley ratio is 2.4 NOT.AND.OR logic gates and Flip-Flop are fabricated using the bistable characteristics of RTDs. Although NOT.AND.OR logic gates need 5~8 transistors. only one RTD is sufficient to fabricate the logic gates. Since the switching time is very short(<10$^12$sec), it is possible to drive the semiconductor circuits fast and integrate them very large. And it is convinced the possibility of integrating RTDs to multilevel logic circuits by observing two peaks of similar current in the serial connection of two RTDs.

• Journal of Power Electronics
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• v.16 no.1
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• pp.227-237
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• 2016

A novel digital current control strategy for digitally controlled DC-DC switching converters, referred to as Adjacent Cycle Sampling (ACS), is proposed in this paper. For the ACS current control strategy, the available time interval from sampling the current to updating the duty ratio, is approximately one switching cycle. In addition, it is independent of the duty ratio. As a result, the contradiction between the processing speed of the hardware and the transient response speed can be effectively relaxed by using the ACS current control strategy. For digitally controlled buck DC-DC switching converters with trailing-edge modulation, digital current control algorithms with the ACS control strategy are derived for three different control objectives. These objectives are the valley, average, and peak inductor currents. In addition, the sub-harmonic oscillations of the above current control algorithms are analyzed and eliminated by using the digital slope compensation (DSC) method. Experimental results based on a FPGA are given, which verify the theoretical analysis results very well. It can be concluded that the ACS control has a faster transient response speed than the time delay control, and that its requirements for hardware processing speed can be reduced when compared with the deadbeat control. Therefore, it promises to be one of the key technologies for high-frequency DC-DC switching converters.