• 제목/요약/키워드: peak current

검색결과 1,752건 처리시간 0.027초

다공성 실리콘의 제조 및 특성에 관한 연구 (Fabrication and Characteristics of Porous Silicon)

  • 이철환;조원일;백지흠;박성용;안춘호;유종훈;조병원;윤경석
    • 한국표면공학회지
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    • 제28권3호
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    • pp.182-191
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    • 1995
  • A highly porous silicon layer was fabricated by anodizing single crystalline silicon in a dilute solution of hydrofluoric acid. The color of the porous silicon changed from red and blue to yellow gold during the anodizing process. The current-voltage (I-V) curve of the anodizing process showed a typical Schottky diode rectification form. The cell voltage decreased with the increase of HF concentration in the solution at high current range. However, the voltage was independent on HF concentration in the solution at low current range. The pore size was dependant on anodizing condition (HF concentration, current and anodizing time). The pore size and wall width of porous silicon layer were 4~6 and 1~3 nm, respectively. Surface of the porous silicon was covered with silicon compound ($SiH_x$etc.) according to IR spectrum analysis. The peak wavelength and width of photoluminescence (PL) spectrum of porous silicon were 650~850 nm (1.5~1.9 eV) and 250 nm, respectively. The photoluminescence intensity and peak wavelength, and porosity of porous silicon increased with increasing anodizing current and decreased with increasing HF concentration in the anodizing solution.

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Current and voltage loading tests off resistive SFCL

  • 최효상;현옥배;김혜림;황시돌;박권배
    • Progress in Superconductivity
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    • 제3권2호
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    • pp.241-246
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    • 2002
  • We have performed the current and voltage loading tests of resistive superconducting fault current limiters (SFCLS) based on $YBa_2$$Cu_3$$O_{7}$(YBCO) films with the diameter of 2 inch. The SFCL consists of meander-type YBCO stripes covered with 200 nm Au layer grown in situ for current shunt and heat dispersion at hot spots. The minimum quench current of an SFCL unit was about 25 Apeak. Seven SFCL units were connected in parallel fur the current load ing tests at power source of 100 $V_{rms}$ $/2,000A_{rms}$. This SFCL units had maximum limiting current of 170 Apeak during the fault instant and then successfully controlled the fault current below 100 Apeak within 1~2 msec after short circuit. Increased short current also reduced the quench completion time with little change of current limiting characterization. We connected six SFCL units in series fur the voltage loading tests at power source of $1,200 V_{rms}$/170 $A_{rms}$ at this time. The shunt resistors were inserted into each SFCL unit to eliminate power imbalance originated from serial connection of SFCL units. Each SFCL unit was quenched simultaneously during the fault condition. The current increased up to 40 $A_{peak}$ and decreased to 14 $A_{peak}$ after 3 cycles. Quench was completed within 1 msec after the fault. We confirmed operating characteristics of 140 kVA($120 A_{rms}$ $\times$ 1,200 $V_{rms}$) SFCL and presented the manufacturing possibility of 3.3 kV SFCL using 4 inch YBCO films.BCO films.lms.

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Effects of acidic pH on voltage-gated ion channels in rat trigeminal mesencephalic nucleus neurons

  • Han, Jin-Eon;Cho, Jin-Hwa;Choi, In-Sun;Kim, Do-Yeon;Jang, Il-Sung
    • The Korean Journal of Physiology and Pharmacology
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    • 제21권2호
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    • pp.215-223
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    • 2017
  • The effects of acidic pH on several voltage-dependent ion channels, such as voltage-dependent $K^+$ and $Ca^{2+}$ channels, and hyperpolarization-gated and cyclic nucleotide-activated cation (HCN) channels, were examined using a whole-cell patch clamp technique on mechanically isolated rat mesencephalic trigeminal nucleus neurons. The application of a pH 6.5 solution had no effect on the peak amplitude of voltage-dependent $K^+$currents. A pH 6.0 solution slightly, but significantly inhibited the peak amplitude of voltage-dependent $K^+$ currents. The pH 6.0 also shifted both the current-voltage and conductance-voltage relationships to the depolarization range. The application of a pH 6.5 solution scarcely affected the peak amplitude of membrane currents mediated by HCN channels, which were profoundly inhibited by the general HCN channel blocker $Cs^+$ (1 mM). However, the pH 6.0 solution slightly, but significantly inhibited the peak amplitude of HCN-mediated currents. Although the pH 6.0 solution showed complex modulation of the current-voltage and conductance-voltage relationships, the midpoint voltages for the activation of HCN channels were not changed by acidic pH. On the other hand, voltage-dependent $Ca^{2+}$ channels were significantly inhibited by an acidic pH. The application of an acidic pH solution significantly shifted the current-voltage and conductance-voltage relationships to the depolarization range. The modulation of several voltage-dependent ion channels by an acidic pH might affect the excitability of mesencephalic trigeminal nucleus neurons, and thus physiological functions mediated by the mesencephalic trigeminal nucleus could be affected in acidic pH conditions.

화재감지센서 활용을 위한 적층헝 PTC서미스터의 특성에 관한 연구 (A Study on the Characteristics of the Multilayer-Type PTC Thermistor for Fire Detection Sensor)

  • 추순남;백동현
    • 한국화재소방학회논문지
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    • 제19권2호
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    • pp.75-80
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    • 2005
  • 적충형 PTC 서미스터의 특성연구를 위해 $(0.90Ba+0.05Sr+0.05Ca)TiO_3+0.01TiO_3+0.01SiO_2+0.0008MnO_2+0.0018Nb_2O_5$와 같은 실험조성식을 설정한 후 표면실장(SMD) 적층형 PTC 시편을 제작하였다. 그 결과 상온 비저항 값을 크게 낮출 수 있고 용도에 따라 전류용량을 크게 할 수 있었으나 적층화로 인해 peak 비저항이 크게 낮아지고 열용량이 커짐으로써 스위칭(switching)시간이 늦어지는 점을 확인하였다. 전압-전류 특성에서는 적층수가 증가할수록 초기 최대전류값이 증가하며 큐리점에 대응하여 저항값이 급격히 커지는 전이전압(전계)도 증가함을 보였다. 그러나 인가전압(전계)을 증가시킬 경우 peak 비저항값을 높일 수 있어 스위칭시간을 줄일 수 있다 이 소자는 화재감지기의 센서로 활용될 수 있다.

$(1-x)(SrPb)(CaMg)TiO_3-xBi_2O_3{\cdot}3TiO_2$ 세라믹의 하전입자 거동에 관한 연구 (A Study on the Behavior of Charged Particles of $(1-x)(SrPb)(CaMg)TiO_3-Bi_2O_3{\cdot}3TiO_2$ Ceramics)

  • 김충혁;최운식;정일형;정규희;이준응
    • 한국전기전자재료학회:학술대회논문집
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    • 한국전기전자재료학회 1992년도 추계학술대회 논문집
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    • pp.34-37
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    • 1992
  • In this paper, the $(SrPb)(CaMg)TiO_3$-xBi_2O_3{\cdot}3TiO_2$ ceramics with paraelectric properties were fabricated by the mixed oxide method. In order to investigate the behavior of charged particles, the characteristics of electrical conduction and thermally stimulated current were measured respectively. As a result on characteristics of the electrical conduction, the leakage current was increased as measuring temperature was increased. At room temperature, the conduction current was divided into the three steps as a function of DC electric field. The first step was Ohmic region due to ionic conduction, below 15[kV/cm]. The second step was showed a saturation which seems to be related to a depolarizing field occuring in field-enforced ferroelectric phase, between 15[kV/cm] and 40[kV/cm]. The third step was attributed to Child's law related to spare charge which injected from electrode, above 40[kV/cm]. Thermally stimulated currents(TSC) spectra with various biasing fields exhibited three distinguished peaks that were denoted as ${\alpha}$, ${\alpha}'$ and ${\beta}$ peak, each of which appeared at nearby -30, 20 and 95[$^{\circ}C$] respectively. It is confirmed that the a peak was due to trap electron trapped in the grainboundary, and ${\alpha}'$ peak that was observed above only 1.5[kV/mm] was attributed to field-enforced ferroelectric polarization. The origin of ${\beta}$ peak was identified as ion migration which caused the degradation.

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Correlation of wind load combinations including torsion on medium-rise buildings

  • Keast, D.C.;Barbagallo, A.;Wood, G.S.
    • Wind and Structures
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    • 제15권5호
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    • pp.423-439
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    • 2012
  • Three common medium- rise building forms were physically tested to study their overall wind induced structural response. Emphasis was placed on the torsional response and its correlation with other peak responses. A higher correlation was found between the peak responses than between the general fluctuating parts of the signals. This suggests a common mechanism causing the peak event, and that this mechanism is potentially different to the mechanism causing the general load fluctuations. The measurements show that about 80% of the peak overall torsion occur simultaneously with the peak overall along wind drag for some generic building shapes. However, the peak torsional response occurs simultaneously with only 30%-40% of the peak overall drag for the rectangular model. These results emphasise the importance of load combinations for building design, which are often neglected in the design of medium sized rigid buildings for which the along-wind drag is dominant. Current design wind loading standards from around the world were evaluated against the results to establish their adequacy for building design incorporating wind-induced torsion effects. Although torsion is frequently neglected, for some structural systems it may become more important.

문턱전압 조절 이온주입에 따른 MCT (MOS Controlled Thyristor)의 스위칭 특성 연구 (Effects of Vth adjustment ion implantation on Switching Characteristics of MCT(MOS Controlled Thyristor))

  • 박건식;조두형;원종일;곽창섭
    • 전자공학회논문지
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    • 제53권5호
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    • pp.69-76
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    • 2016
  • MCT (MOS Controlled Thyristor)의 전류 구동능력은 도통상태의 MCT를 턴-오프 시킬 수 있는 능력, 즉 off-FET의 성능에 의해 결정되고, MCT의 주된 응용분야인 펄스파워 분야에서는 턴-온 시의 피크전류($I_{peak}$)와 전류상승기울기(di/dt) 특성이 매우 중요하다. 이러한 요구사항을 만족시키기 위해서는 MCT의 on/off-FET 성능 조절이 중요하지만, 깊은 접합의 P-웰과 N-웰을 형성하기 위한 삼중 확산공정과 다수의 산화막 성장공정은 이온주입 불순물의 표면농도를 변화시키고 on/off-FET의 문턱전압($V_{th}$) 조절을 어렵게 한다. 본 논문에서는 on/off-FET의 $V_{th}$를 개선하기 위한 채널영역 문턱전압 이온주입에 대하여 시뮬레이션을 진행하고 이를 토대로 제작한 MCT의 전기적 특성을 비교 평가하였다. 그 결과 문턱전압 이온주입을 진행한 MCT의 경우(활성영역=$0.465mm^2$) $100A/cm^2$ 전류밀도에서의 전압손실($V_F$)은 1.25V, 800V의 어노드 전압에서 $I_{peak}$ 및 di/dt는 290A와 $5.8kA/{\mu}s$로 문턱전압 이온주입을 진행하지 않은 경우와 유사한 특성을 나타낸 반면, $100A/cm^2$의 구동전류에 대한 턴-오프 게이트전압은 -3.5V에서 -1.6V로 감소하여 MCT의 전류 구동능력을 향상시킴을 확인하였다.

인버터 용접기의 전압손실 개선에 관한 연구 (On Study for Improvement of The Inverter Welder)

  • 배종일;이동철
    • 대한전기학회:학술대회논문집
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    • 대한전기학회 2006년도 제37회 하계학술대회 논문집 D
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    • pp.2063-2064
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    • 2006
  • The power source of inverter welder stable power of low voltage and high current. Because if shouldn't be, it is caused to spark between the parent metal and the peak. So that, we designed to be base on high frequency transformer and reactor of DC part. Then, we optimized control of PWM, current rising slant, voltage, current, pulse current and inverter out-put voltage. Also we designed PCB for EMI and noises.

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CMOS Inverter의 Substrate Current를 줄이는 Layout 설계 (New Layout Design Concept for Suppressing the Substrate Current in CMOS Inverter)

  • 박흥준;김충기
    • 대한전기학회:학술대회논문집
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    • 대한전기학회 1987년도 전기.전자공학 학술대회 논문집(I)
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    • pp.407-410
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    • 1987
  • A layout design concept which suppress the substrate current generated during the switching transients of an CMOS inverter is presented. The amount of hot carriers and the peak value of substrate current can be reduced by changing the device geometry ratio of driver and load device of an CMOS inverter.

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SEMS와 고립동기 발전기 병렬 운전

  • 손수국
    • ETRI Journal
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    • 제6권4호
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    • pp.37-40
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    • 1984
  • in the case of using SMES to shave the peak load with the isolated synchronous ge nerator- converter, the performance equations are derived. The commutation angle, the power angle, the field current, the storage energy and the power are derived by changing firing angle, that is, following the excitation velocity of SMES current. The output characteristics are computed by digital computer simulation.

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