• Journal of the Korean Society of Manufacturing Technology Engineers
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• v.24 no.1
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• pp.135-139
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• 2015

We present a fine patterning method of conductive lines on polyimide (PI) and glass substrates using silver (Ag) nanoparticles based on laser scanning. Controlled laser irradiation can realize selective sintering of conductive ink without damaging the substrate. Thus, this technique easily creates fine patterns on heat-sensitive substrates such as flexible plastics. The selective laser sintering of Ag nanoparticles was managed by optimizing the conditions for the laser scan velocity (1.0-20 mm/s) and power (10-150 mW) in order to achieve a small gap size, high electrical conductivity, and fine roughness. The fabricated electrodes had a minimum channel length of $5{\mu}m$ and conductivity of $4.2{\times}10^5S/cm$ (bulk Ag has a conductivity of $6.3{\times}10^5S/cm$) on the PI substrate. This method was used to successfully fabricate an organic field effect transistor with a poly(3-hexylthiophene) channel.

• Korean Journal of Materials Research
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• v.26 no.11
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• pp.635-643
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• 2016

Graphene has shown exceptional properties for high performance devices due to its high carrier mobility. Of particular interest is the potential use of graphene nanoribbons as field-effect transistors. Herein, we introduce a facile approach to the fabrication of graphene nanoribbon (GNR) arrays with ~200 nm width using nanoimprint lithography (NIL), which is a simple and robust method for patterning with high fidelity over a large area. To realize a 2D material-based device, we integrated the graphene nanoribbon arrays in field effect transistors (GNR-FETs) using conventional lithography and metallization on highly-doped $Si/SiO_2$ substrate. Consequently, we observed an enhancement of the performance of the GNR-transistors compared to that of the micro-ribbon graphene transistors. Besides this, using a transfer printing process on a flexible polymeric substrate, we demonstrated graphene-silicon junction structures that use CVD grown graphene as flexible electrodes for Si based transistors.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2003.07a
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• pp.370-373
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• 2003

As the integrated circuit device shrinks to the smaller dimension, the chemical mechanical polishing (CMP) process was required for the global planarization of inter-metal dielectric(IMD) layer with free-defect. However, as the IMD layer gets thinner, micro-scratches are becoming as major defects. Chemical-Mechanical Planarization(CMP) of conductors is a key process in Damascene patterning of advanced interconnect structure. The effect of alternative commerical slurries pads, and post-CMP cleaning alternatives are discuess, with removal rate, scratch dentisty, surface roughness, dishing, erosion and particulate density used as performance metrics. Electroplated copper depostion is a mature process from a historical point of view, but a very young process from a CMP persperspective. While copper electrodepostion has been used and stuidied for dacades, its application to Cu damascene wafer processing is only now ganing complete accptance in the semiconductor industry. The polishing mechanism of Cu CMP process has been reported as the repeated process of passive layer formation by oxidizer and abrasion action by slurry abrasives. however it is important to understand the effect of oxidizer on copper pasivation layer in order to obtain higher removal rate and non-uniformity during Cu-CMP process. In this paper, we investigated the effects of oxidizer on Cu-CMP process regarding the additional volume of oxidizer.

• Journal of the Semiconductor & Display Technology
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• v.10 no.4
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• pp.53-59
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• 2011

Recently there have been considerable attentions on nanoimprint lithography (NIL) by the display device and semiconductor industry due to its potential abilities that enable cost-effective and high-throughput nanofabrication. Although one of the current major research trends of NIL is large-area patterning, the technical difficulties to keep the uniformity of the residual layer become severer as the imprinting area increases more and more. In this paper we focused on the deformation of the $2^{nd}$ generation TFT-LCD sized ($370{\times}470mm^2$) large-area soft mold in the UV imprinting process. A mold was fabricated with PDMS(Poly-dimethyl Siloxane) layered glass back plate(t0.5). Besides, the mold includes large surrounding wall type protrusions of 1.9 mm width and the via-hole(7 ${\mu}m$ diameter) patterend area. The large surrounding wall type protrusions cause the proximity effect which severely degrades the uniformity of residual layer in the via-hole patterend area. Therefore the deformation of the mold was calculated by finite element analysis to assess the effect of large surrounding wall type protrusions and the flexiblity of the mold. The deformation of soft mold was verified by the measurements qualitatively.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2004.07a
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• pp.20-23
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• 2004

As the integrated circuit device shrinks to the smaller dimension, the chemical mechanical polishing(CMP) process was required for the global planarization of inter-metal dielectric(IMD) layer with free-defect. However, as the IMD layer gets thinner, micro-scratches are becoming as major defects. Chemical-Mechanical polishing(CMP) of conductors is a key process in Damascene patterning of advanced interconnect structure. The effect of alternative commercial slurries pads, and post-CMP cleaning alternatives are discuss, with removal rate, scratch dentisty, surface roughness, dishing, erosion and particulate density used as performance metrics. Electroplated copper deposition is a mature process from a historical point of view, but a very young process from a CMP perspective. While copper electro deposition has been used and studied for decades, its application to Cu damascene wafer processing is only now gaining complete acceptance in the semiconductor industry. The polishing mechanism of Cu-CMP process has been reported as the repeated process of passive layer formation by oxidizer and abrasion action by slurry abrasives. however it is important to understand the effect of oxidizer on copper passivation layer in order to obtain higher removal rate and non-uniformity during Cu-CMP process. In this paper, we investigated the effects of oxidizer on Cu-CMP process regarding the additional volume of oxidizer.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.27 no.12
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• pp.871-876
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• 2014

Efficiency of crystalline Si solar cell can be maximized as minimizing optical loss through antireflection texturing with inverted pyramids. Even if cost-competitive, soft lithography can be employed instead of photolithography for the purpose, some limitations still remain to apply the soft lithography directly to as-received solar grade wafer with a bunch of micro trenches on surface. Therefore, it is needed to develop a low-cost, effective planarization process and evaluate its output to be applicable to patterning process with PDMS stamp. In this study new surface planarization process is proposed and the change of micro scale trenches on the surface as a function of etching time is observed. Also, the effect of trenches on pattern quality by soft lithography is investigated using FEM structural analysis. In conclusion it is clear that the geometry and shape of trenches would be basic considerations for soft lithography application to low quality wafer.

• Journal of the Korean Vacuum Society
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• v.15 no.1
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• pp.97-102
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• 2006

Anodic alumina with self-organized and ordered nano hole arrays can be a good candidate of an irradiation mask to modify the properties of nano-scale region. In order to try using porous anodic alumina as a mask for ion-beam patterning, ion beam transmittance of anodic alumina was tested. 4 Um thick self-standing AAO templates anodized from Al bulk foil with two different aspect ratio, 200:1 and 100:1, were aligned about incident ion beam with finely controllable goniometer. At the best alignment, the transmittance of the AAO with aspect ratio of 200:1 and 100:1 were $10^{-8}\;and\;10^{-4}$, respectively. However transmittance of the thin film AAO with low aspect ratio, 5:1, were remarkably improved to 0.67. The ion beam transmittance of self-standing porous alumina with a thickness larger than $4{\mu}m$ is extremely low owing to high aspect ratio of nano hole and charging effect, even at a precise beam alignment to the direction of nano hole. $SiO_2$ nano dot array was formed by ion irradiation into thin film AAO on $SiO_2$ film. This was confirmed by scanning electron microscopy that the $SiO_2$ nano dot array is similar to AAO hole array.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.31 no.3
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• pp.129-134
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• 2018

Herein, we report the manufacture of high-performance, ambipolar organic field-effect transistors (OFETs) and complementary-like electronic circuitry based on a blended, polymeric, semiconducting film. Relatively high and well-balanced electron and hole mobilities were achieved by incorporating a small amount of ionic additives. The equivalent P-channel and N-channel properties of the ambipolar OFETs enabled the manufacture of complementary-like inverter circuits with a near-ideal switching point, high gain, and good noise margins, via a simple blanket spin-coating process with no additional patterning of each active P-type and N-type semiconductor layer.

• Proceedings of the Korean Vacuum Society Conference
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• 2016.02a
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• pp.410.1-410.1
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• 2016

Vanadium dioxide ($VO_2$) is a well-known material that exhibits a metal-semiconductor transition at 340 K, with drastic change of transmittance at NIR region. However, $VO_2$ based thermochromics accompany with low visible transmittance value and unfavorable color (brownish yellow). Herein, we demonstrate the adjustment of visible transmittance of $VO_2$ thin film by nanosphere template assisted patterning process using sol-gel method. 2-Dimenstional honeycomb shape was varied as function of diameter of nanosphere and coating conditions. The morphological geometry of the films was investigated by FE-SEM and AFM. Result shows that inversed shape of nanosphere was formed clearly and pattern width was altered according to the bead size. This structure creates the geometrical blank area from the position of nanosphere which improves the optical transmittance at the visible region. Moreover, such patterned $VO_2$ thin film not only maintains the optical switching efficiency, but also generate the gorgeous scattering effect which presumably support the glazing application.

• Proceedings of the Korean Vacuum Society Conference
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• 2013.02a
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• pp.687-687
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• 2013

In rearpoint contact solar cell and the PERC (passivated emitter rear contact) type cell, surfaces were passivated by SiO2 or Al2O3 to increase solar cell efficiency. Therefore, we have investigated the effect of surface passivation for crystalline silicon solarcell using mass-production atomic layer deposited (ALD) Al2O3. The patttern which consists of cylinders with 100um diameter and 5um height was formed by PR patterning on Si (100) substrate and then Al2O3 of about 10nm and 20nm thickness was deposited by ALD. The pattern in 10 nm Al2O3 film was removed by dipping in aceton solution for about 10 min but the pattern in 20 nm Al2O3 film was not. The influences of process temperature and heat treatment were investigated using microwave photoconductance decay (PCD) and Quasi-Steady-State photoconductance (QSSPC). The solar cell process used in this work combines the advantage of using the applicability of a selective deposition associated with a ALD passivation and the use of low-cost screen print for the contacts formation.