• The KIPS Transactions:PartA
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• v.10A no.1
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• pp.25-34
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• 2003

Parallel file system solves I/O bottleneck to store a file distributedly and read it parallel exchanging messages among computers that is connected multiple computers with high speed networks. However, they do not consider the message characteristics and performances are decreased. Accordingly, the current study proposes the Hybrid Channel model (HCM) as a message-management method, whereby the messages of a parallel file system are classified by a message characteristic between control messages and file data blocks, and the communication channel is divided into a message channel and data channel. The message channel then transfers the control messages through TCP/IP with reliability, while the data channel that is implemented by Virtual Interface Architecture (VIA) transfers the file data blocks at high speed. In tests, the proposed parallel file system that is implemented by HCM exhibited a considerably improved performance.

• 제어로봇시스템학회:학술대회논문집
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• 2003.10a
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• pp.1424-1429
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• 2003

In this paper, the design method of sliding mode control (SMC) system for SISO linear system is discussed. First, we consider the similarity between the design method of sliding mode hyper plane using the strict positive realness and the characteristics of zeros of feedback system and the design method of simple adaptive control. Based on such a consideration, we propose the new design method of SMC system using parallel dynamic compensator. As a result, SMC system can be constructed only with the derivative of output signal for controlled plant. The performance of SMC system designed by proposed method is confirmed through the numerical example.

• Proceedings of the IEEK Conference
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• 2002.07a
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• pp.149-151
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• 2002

We had been developing the variety of parallel processing systems in order to improve the processing speed of visual media applications. These systems were using multi-access memory system(MAMS) as a parallel memory system, which provides the capability of the simultaneous accesses of image points in a line-segment with an arbitrary degree, which is required in many low-level image processing operations such as edge or line detection in a particular direction, and so on. But, the performance of these systems did not give a faithful speed because of asynchronous feature between MAMS and processing elements. To improve the processing speed of these systems, we have been investigated a pipelined parallel processing system using MAMS. Although the system is considered as being the single instruction multiple data(SIMD) type like the early developed systems, the performance of the system yielded about 2.5 times faster speed.

• Proceedings of the KIEE Conference
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• 2006.04b
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• pp.372-375
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• 2006

This paper proposes a parallel operation system of the Z-source active power filter using one fuel cells(FC) system. The proposed system is composed of two Z-source inverters operating in parallel only one PEM(Polymer Electrolyte Membrane)FC system. Also, as the control algorithm of the active power filter, a single phase P-Q theory and PI control are adopted. The effectiveness of the proposed the system is verified by the PSIM simulation in the steady state and the transient state.

• 한국신재생에너지학회:학술대회논문집
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• 2008.05a
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• pp.65-68
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• 2008

This paper proposes the parallel operation control algorithm of a power conditioning system (PCS) for a distributed Fuel Cell power generation system. A proposed control algorithm is made good a drawback of the conventional control algorithm. The controller must also supervise the total PCS operation while communicating with the fuel cell system controller. Simulation results are presented to performance of a proposed control algorithm for the PCS.

• Journal of the Korea Society for Simulation
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• v.3 no.1
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• pp.29-42
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• 1994

The architecture of a MIMD-type parallel computer system is specified: a simulator is developed to support design and evaluation of systems based on the architecture: and conducted with the simulator to evaluate system performance. The horizontal/vertical-bus(H/V-bus) system architecture provides an NxN array of processing elements which communicate with each other through a network of N horizontal buses and N vertical buses. The simulator, written in SLAM II and FORTRAN, is designed to provide high-resolution in simulating the IPC mechanism. Parameters provide the user with independent control of system size, PE speed and IPC mechanism speed. Results generated by the simulator include execution times, PE utilizations, queue lengths, and other data. The simulator is used to study system performance when a partial differential equation is solved by parallel Gauss-Seidel method. For comparisons, the benchmark is also executed on a single-bus system simulator that is derived from the H/V-bus system simulator. The benchmark is also solved on a single PE to obtain data for computing speedups. An extensive analysis of results is presented.

• International Journal of Reliability and Applications
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• v.8 no.1
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• pp.67-82
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• 2007

This paper deals with the effectiveness analysis of an engineering system, which has two units of different strengths in parallel and one unit as a cold standby unit. Failure times for all the units have negative exponential distribution whereas their repair times have general distribution. Single server caters the need for the system. The effectiveness analysis of the system is done by using regenerative point technique. The different measures of effectiveness such as mean sojourn time, mean time to system failure, availability, busy period, etc, are derived. Cost factors also taken into consideration.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.11
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• pp.130-138
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• 2016

In this paper present the real-time system parallel testing techniques for weapon systems error verification. Previously field testing equipment in the military field was using the sequential testing method to maintain. This method could not check the error verification of interference. For this reason, in this paper propose the real-time system parallel testing techniques using an embedded module instead of the sequential testing techniques which is used in the weapon system error verification. Using the embedded module mounted switching control card conduct the parallel testing and then send the result to the PC. This method is possible to increase the reliability in the weapon system error verification.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.14 no.1
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• pp.138-144
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• 2010

Tachyon primary system which introduces recently is a high performance supercomputer that composed with AMD Barcelona nodes. In this paper, we will verify the performance and parallel scalability of TachyonIn by using multi-zone NAS Parallel Benchmark(NPB) which is one of a program with hybrid parallel method. To test performance of hybrid parallel execution, B and C classes of BT-MZ in NPB version 3.3 were used. And the parallel scalability test has finished with Tachyon's 1024 processes. It is the first time in Korea to get a result of hybrid parallel computing calculation using more than 1024 processes. Hybrid parallel method in high performance computing system with multi-core technology like Tachyon describes that it can be very efficient and useful parallel performance benchmarks.

• Proceedings of the IEEK Conference
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• 2001.06c
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• pp.29-32
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• 2001

In this paper, we applied the high-performance PGAP(Parallel Genetic Algorithm Processor) to recognizing rotated pattern. In order to perform this research efficiently, we used Multi-PGAP system consisted of four PGAP. In addition, we used mental rotation based on the rotated pattern recognition mechanism of human to reduce the number of operation. Also, we experimented with distinguishing specific pattern from similar coin patterns and determine rotated angle between patterns. The result showed that the development of future artificial recognition system is feasible by employing high performance PGAPS.