• The Transactions of The Korean Institute of Electrical Engineers
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• v.65 no.4
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• pp.666-672
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• 2016

Recently the fingerprint is widely used as one of biometrics to improve the security of financial mobile applications, because of its user convenience and high recognition rate. However, in order to apply fingerprint algorithms to finance and security applications, the recognition rate and processing speed of the fingerprint algorithms have to be improved further. In this paper, we propose the parallel fingerprint enhancement algorithm on general-purpose computing on graphics processing unit (GPGPU) using OpenCL. We discuss the analysis of the parallelism in the fingerprint algorithm as well as the exploration of optimization parameters of the parallel fingerprint algorithm to improve the performance. The experimental results showed that the execution of parallel fingerprint enhancement algorithm on GPGPUs was accelerated from 29.4 upto 69.2 times compared with the execution of the original one on the host CPUs.

• Journal of the Korea Society of Computer and Information
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• v.19 no.12
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• pp.1-10
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• 2014

This paper proposes a scheduling scheme that enhances power consumption efficiency of periodic real-time tasks using DVFS and power-shut-down mechanisms while meeting their deadlines on multicore processors. The proposed scheme is suitable for dependent multicore processors in which processing cores have an identical speed at an instant, and resolves the load unbalance of processing cores by exploiting parallel processing because the load unbalance causes inefficient power consumption in previous methods. Also the scheme activates a part of processing cores and turns off the power of unused cores. The number of activated processing cores is determined through mathematical analysis. Evaluation experiments show that the proposed scheme saves up to 77% power consumption of the previous method.

• The Transactions of the Korea Information Processing Society
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• v.6 no.4
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• pp.901-915
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• 1999

Parallel computers are known to be excellent in performance per cost also satisfying scalability and high performance. However parallel machines have enjoyed limited success because of difficulty in parallel programming and non-portability between parallel machines. Recently, researchers have sought to develop data parallel language that provides machine independent programming systems. Data parallel language such as High Performance Fortran provides a basis to write a parallel program based on a global name space by partitioning data and computation, generating message-passing function. In this paper, we describe the Parallel Programming Translator(PPTran), source-to-source data parallel compiler, generating MPI SPMD parallel program from HPF input program through four phases such as data dependence analysis, partitioning data, partitioning computation, and code generation with explicit message-passing and verify the performance of PPTran

• The Transactions of the Korea Information Processing Society
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• v.6 no.7
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• pp.1756-1769
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• 1999

Parallel paths in an interconnection network have some significance in that message transmission time can be reduced because message is divided into packets and transmitted in parallel through several paths, and also an whose nodes has 2n binary bit string, is an interconnection network which has a lower network cost than hypercube and its variation. In this paper, we analyze node disjoint parallel path in Folded Hyper-Star graph FHS(2n,n) proposed as the topology of parallel computers and, using the result, prove that the fault diameter of a Folded Hyper-Star graph FHS(2n,n) is 2n-1.

• Proceedings of the Korea Information Processing Society Conference
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• 2006.11a
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• pp.161-164
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• 2006

인터넷이 발전하면서 웹에는 같은 내용을 다양한 언어로 표현한 문서들이 많이 존재한다. 이와 같은 웹 문서의 성질을 이용하여, 이 논문은 웹으로부터 수집된 병렬문서(parallel document)를 이용하여 한영 병렬말뭉치 구축 시스템을 설계하고 구현한다. 이 논문에서 구축과정을 요약하면 다음과 같다. 첫째, 웹 문서수집기를 이용해서 웹으로부터 한영 웹문서(html 문서)를 각각 수집한다. 둘째, 수집된 각 언어의 웹 문서에서 불필요한 내용(태그와 광고 문구 등)을 제거하여 문장을 추출하고, 추출된 문장을 단락단위로 정렬한다. 셋째, 단락단위로 정렬된 문서를 문장정렬(sentence alignment) 방법을 이용해서 문장을 정렬한다. 끝으로 정렬된 병렬문장을 단어 단위로 분리하여 병렬말뭉치를 구축한다. 이와 같은 방법으로 이 논문에서는 약 42만 5천 문장의 한영 병렬말뭉치를 구축하였다.

• Proceedings of the Korea Information Processing Society Conference
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• 2011.04a
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• pp.250-253
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• 2011

Chip manufacture nowadays turned their attention from accelerating uniprocessors to integrating multiple cores on a chip. Moreover desktop graphic hardware is now starting to support general purpose computation. Desktop users are able to use multi-core CPU and GPU as a high performance computing resources these days. However exploiting parallel computing resources are still challenging because of lack of higher programming abstraction for parallel programming. The 2-dimensional discrete cosine transform (2D-DCT) algorithms are most computational intensive part of JPEG encoding. There are many fast 2D-DCT algorithms already studied. We implemented several algorithms and estimated its runtime on multi-core CPU and GPU environments. Experiments show that data parallelism can be fully exploited on CPU and GPU architecture. We expect parallelized DCT bring performance benefit towards its applications such as JPEG and MPEG.

• Journal of applied mathematics & informatics
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• v.5 no.2
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• pp.427-432
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• 1998

When an undirected tree T and a vertex ${\gamma}$ in the tree are given the problem to transform T into a rooted tree with ${\gamma}$ as its root is considered. Using Euler tour and prefix sum an optimal algorithm has been developed [2,3]. We will present another parallel algorithm which is optimal also on EREW PRAM. Our approach resuces the given tree step by step by pruning and pointer jumping. That is the tree structure is retained during algorithm processing such that than other tree computations can be carried out in parallel.

• Journal of the Korea Society of Computer and Information
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• v.16 no.10
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• pp.11-21
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• 2011

This paper introduces an SIMD(Single Instruction Multiple Data) based parallel processor that efficiently processes massive data inherent in multimedia. In addition, this paper implements MMX(MultiMedia eXtension)-type instructions on the data parallel processor and evaluates and analyzes the performance of the MMX-type instructions. The reference data parallel processor consists of 16 processors each of which has a 32-bit datapath. Experimental results for a JPEG compression application with a 1280x1024 pixel image indicate that MMX-type instructions achieves a 50% performance improvement over the baseline instructions on the same data parallel architecture. In addition, MMX-type instructions achieves 100% and 51% improvements over the baseline instructions in energy efficiency and area efficiency, respectively. These results demonstrate that multimedia specific instructions including MMX-type have potentials for widely used many-core GPU(Graphics Processing Unit) and any types of parallel processors.

• Journal of the Korea Society of Computer and Information
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• v.26 no.1
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• pp.155-161
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• 2021

Recently, researches for military purposes such as precision tracking and mission completion using UAVs have been actively conducted. In particular, if the posture information of the leading UAV is estimated and the mission UAV uses this information to follow in stealth and complete its mission, the speed of the posture information estimation of the guide UAV must be processed in real time. Until recently, research has been conducted to accurately estimate the posture information of the leading UAV using image processing and Kalman filters, but there has been a problem in processing speed due to the sequential processing of the processing process. Therefore, in this study we propose a way to improve processing speed by applying methods that the image processing area is limited to the ROI area including the object, not the entire area, and the continuous processing is distributed to OpenMP-based multi-threads and processed in parallel with thread synchronization to estimate attitude information. Based on the experimental results, it was confirmed that real-time processing is possible by improving the processing speed by more than 45% compared to the basic processing, and thus the possibility of completing the mission can be increased by improving the tracking and estimating speed of the mission UAV.

• Journal of the Institute of Electronics and Information Engineers
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• v.54 no.4
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• pp.75-80
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• 2017

ES (Electronic Warfare Support System) collects radar signals, and analyzes the signals about frequency, pulse width, PRI (Pulse Repetition Interval), and etc. and then ES compares analyzed result with known radar signals to identify them. But there are two disadvantage. One is that use of known radar signals is in comparing step only. The other is that calculating PRI needs many operations. In this paper proposes a parallel reference correlation algorithm that uses GPGPU (General Purpose Graphics Processing Units) and can identify what signals are in received radar signals without calculating PRI.