• Journal of KIISE:Computing Practices and Letters
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• v.8 no.1
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• pp.9-16
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• 2002

Join operation exert a great effect on the performance of system in temporal database as in the relational database. Especially, as for the temporal join, the optimization of interval partition decides the performance of query processing. In this paper, to improve the efficiency of parallel join query in temporal database. I proposed Minimum Interval Partition(MIP) scheme that time interval partitioning. The validity of this MIP algorithm that decides minimum breakpoint of the partition is proved by example scenario and I confirmed improved efficiency as compared with existing partition algorithm.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.10
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• pp.46-52
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• 2009

A Multi-Core/Multi-Thread architecture is adopted for the Shader processor to enhance the processing performance. The Shader processor is designed to utilize its processing core IP for multiple purposes, such as Vertex-Shading, Rasterization, Pixel-Shading, etc. In this paper, we propose a 'Rasterization based on Vector Algorithm' that makes parallel pixels processing possible with Multi-Core and Multi-Thread architecture on the Shader Core. The proposed algorithm takes only 2% operation counts of the Scan-Line Algorithm and processes pixels independently.

• The Transactions of the Korean Institute of Power Electronics
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• v.24 no.5
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• pp.379-387
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• 2019

A bidirectional flyback converter is a suitable topology for use in a PV-to-bus differential power processing (DPP) module for PV applications due to its electrical isolation capability, bidirectional power transfer, high step-up ratio, and simple circuit structure. However, the bidirectional flyback converter design should consider the effect of the output-side power switch utilized for bidirectional operation compared with that of the conventional flyback converter. This study presents the structure and design methodology of the bidirectional flyback converter for a PV DPP module. Magnetizing inductance is designed by calculating the power loss of converter components within the rated load range under the discontinuous conduction mode, which is unaffected by the reverse recovery characteristics of the anti-parallel diode of the output-side power switch. The validity of the proposed design methodology is verified using a 25 W bidirectional flyback converter prototype. The operational principles and the performance of the DPP operation are verified using practical DPP modules consisting of bidirectional flyback converters implemented according to the proposed design methodology.

• The Transactions of the Korea Information Processing Society
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• v.4 no.1
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• pp.288-297
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• 1997

Real-time video multicast using a single computer system is a difficult task because capturing, compressing and delivering video causes a long delay in internetworking environments. This paper describes an implementation of the real time video multicasting server which processes video capture, compression and multicasting in parallel. This paper also presents a flow control mechanism to solve a problem caused by difference between the three tasks.

• Journal of KIISE:Databases
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• v.29 no.1
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• pp.44-57
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• 2002

Multiple spatial queries are defined as two or more spatial range queries to be executed at the same time. The primary processing of internet-based map services is to simultaneously execute multiple spatial queries. To improve the throughput of multiple queries, the time of disk I/O in processing spatial queries significantly should be reduced. The declustering scheme of a spatial dataset of the MIMD architecture cannot decrease the disk I/O time because of random seeks for processing multiple queries. This thesis presents query scheduling strategies to ease the problem of inter-query random seeks. Query scheduling is achieved by dynamically re-ordering the priority of the queued spatial queries. The re-ordering of multiple queries is based on the inter-query spatial relationship and the latency of query processing. The performance test shows that the time of multiple query processing with query scheduling can be significantly reduced by easing inter-query random seeks as a consequence of enhanced hit ratio of disk cache.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2007.10a
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• pp.607-610
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• 2007

In this paper, proposes the monitoring system it will be able to trace the executed of each threads in OpenMP based a parallel program. The monitoring system of existing in uses each threads label information and the analysis technique which uses the access-history was most. This has the problem which raises the time and space complexity which is caused by with massive information creation. In this paper, only the thread which includes interest information it creates tracking information with the target. And it provides information which is intuitive to the user it provides the visualization system for to a same time. The visualization model is composed the images-information of a base. This does to be it will be able to understandable a program execute situation using an image processing technique. Therefore, this paper provides the parallel program an effective debugging environment.

• The Transactions of the Korea Information Processing Society
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• v.5 no.4
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• pp.883-891
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• 1998

This paper proposes a scheme to exploit SIMD parallelism in the simulation of Cellular Automata models. The basic idea is to increase the utilization of an ALU in the underlying computer and to reduce simulation time by exploiting the parallelism. Thus, several cells are packed into a computer word and transit their state together. To show the performance of the proposed simulation scheme, two Cellular Automata models are simulated under three distinct hardware environments. The results show considerably high simulation speed-up for every case. Especially, the simulation speedup with the proposed simulation scheme reaches nearly 20 times in the best case.

• Proceedings of the Korea Multimedia Society Conference
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• 2012.05a
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• pp.343-344
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• 2012

With the increase of sensitive data and their secure transmission and storage, the use of encryption techniques has become widespread. The performance of encoding majorly depends on the computational time, so a system with less computational time suits more appropriate as compared to its contrary part. Double Random Phase Encoding (DRPE) is an algorithm with many sub functions which consumes more time when executed serially; the computation time can be significantly reduced by implementing important functions in a parallel fashion on Graphics Processing Unit (GPU). Computing convolution using Fast Fourier transform in DRPE is the most important part of the algorithm and it is shown in the paper that by performing this portion in GPU reduced the execution time of the process by substantial amount and can be compared with MATALB for performance analysis. NVIDIA graphic card GeForce 310 is used with CUDA C as a programming language.

• IEIE Transactions on Smart Processing and Computing
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• v.5 no.4
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• pp.289-293
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• 2016

As more mobile devices are equipped with multi-core CPUs and are required to execute many compute-intensive multimedia applications, it is important to optimize the systems, considering the underlying parallel hardware architecture. In this paper, we implement and optimize ray-tracing application tailored to a given mobile computing platform with multiple heterogeneous processing elements. In this paper, a lightweight ray-tracing application is specified and implemented in Kahn process network (KPN) model-of-computation, which is known to be suitable for the description of real-time applications. We take an open-source C/C++ implementation of ray-tracing and adapt it to KPN description in the Distributed Application Layer framework. Then, several possible configurations are evaluated in the target mobile computing platform (Exynos 5422), where eight heterogeneous ARM cores are integrated. We derive the optimal degree of parallelism and a suitable distribution of the replicated tasks tailored to the target architecture.

• The Transactions of the Korea Information Processing Society
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• v.7 no.4
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• pp.1201-1210
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• 2000

In order to tolerate faults which may occur during the execution of distributed tasks in high-performance parallel computer systems, tasks are duplicated on different processors. In this paper, by utilizing the task duplication based scheduling algorithm, a new task scheduling algorithm which duplicates each task on more than two different processors with the minimum schedule length is presented, and the number of processors required for the duplication is analyzed with the ratio of communication cost to computation time and the workload of the system. A simulation with various task graphs reveals that the number of processors required for the full-duplex fault-tolerant task scheduling with the obtainable minimum schedule length increases about 30% to 75% when compared with that of the task duplication based scheduling algorithm.