• 대한전기학회:학술대회논문집
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• 대한전기학회 2001년도 학술대회 논문집 전문대학교육위원
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• pp.134-140
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• 2001

Parallel processing has the potential to be cost effectively used on computationally intense power system problems. But this technology is not still available is not only parallel computer but also parallel processing scheme. Testing these algorithms to ensure accuracy, and evaluation of their performance is also an issue. Although a significant amount of parallel algorithms of power system problem have been developed in last decade, actual testing on processor architectures lies in the beginning stages. This paper presents the parallel processing algorithm to supply the base being able to treat power flow by newton's method by the distributed memory type parallel computer. This method is to assign and to compute teared blocks of sparse matrix at each parallel processors. The testing to insure accuracy of developed method have been done on serial computer by trying to simulate a parallel environment.

• 전기학회논문지P
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• 제51권2호
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• pp.55-59
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• 2002

Parallel processing is able to be used effectively on computationally intense power system problems. But this technology is not still available is not only parallel computer but also parallel processing scheme. Testing these algorithms to ensure accuracy, and evaluation of their performance is also an issue. Although a significant amount of parallel algorithms of power system problem have been developed in last decade, actual testing on parallel computer architectures lies in the beginning stages because no clear cut paths. This paper presents Jacobian modeling method to supply the base being able to treat power flow by newton's method by the computer. This method is to assign and to compute teared blocks of sparse matrix at each parallel processors. The testing to insure accuracy of developed method have been done on serial computer by trying to simulate a parallel environment.

• International journal of advanced smart convergence
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• 제8권4호
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• pp.194-199
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• 2019

As the performance of the system increases, more parallelized data is being processed than single processing of data. Today's cpu structure has been developed to leverage multicore, and hence data processing methods are being developed to enable parallel processing. In recent years desktop cpu has increased multicore, data is growing exponentially, and there is also a growing need for data processing as artificial intelligence develops. This neural network of artificial intelligence consists of a matrix, making it advantageous for parallel processing. This paper aims to speed up the processing of the system by using raspberrypi to implement the cluster building and parallel processing system against the backdrop of the foregoing discussion. Raspberrypi is a credit card-sized single computer made by the raspberrypi Foundation in England, developed for education in schools and developing countries. It is cheap and easy to get the information you need because many people use it. Distributed processing systems should be supported by programs that connected multiple computers in parallel and operate on a built-in system. RaspberryPi is connected to switchhub, each connected raspberrypi communicates using the internal network, and internally implements parallel processing using the Message Passing Interface (MPI). Parallel processing programs can be programmed in python and can also use C or Fortran. The system was tested for parallel processing as a result of multiplying the two-dimensional arrangement of 10000 size by 0.1. Tests have shown a reduction in computational time and that parallelism can be reduced to the maximum number of cores in the system. The systems in this paper are manufactured on a Linux-based single computer and are thought to require testing on systems in different environments.

• 전기전자학회논문지
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• 제4권2호
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• pp.212-224
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• 2000

본 논문에서는 영상 응용프로그램의 처리 속도를 향상하기 위한 병렬처리 시스템을 제안한다. 병렬처리 시스템은 Pipelined SIMD 구조를 갖고 있으며, 다수개의 처리기와 다중접근 기억장치로 구성된다. 다중접근 기억장치는 메모리 모듈들과 메모리 제어부로 구성되며, 메모리 제어부는 메모리 모듈 선택 모듈, 데이터 라우팅 모듈, 그리고 주소 계산 및 라우팅 모듈로 구성되어 있으며, 블록, 행, 그리고 열 내의 데이터를 동시에 접근할 수 있는 기능을 제공한다. 제안한 병렬처리 시스템을 검증하기 위해서 형태학적 필터를 적용하여 기능 검증 및 처리속도를 확인하였다.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1988년도 전기.전자공학 학술대회 논문집
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• pp.647-650
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• 1988

This paper proposes and sketches out a new parallel architecture of transputer-based pyramidal parallel array computer (TPPAC) used to process computationally intensive problems for geometric processing applications such as computer vision, image processing etc. It explores how efficiently the pyramid computer architecture is designed using transputer chips, and poses a new interconnection scheme for TPPAC without using additional transputers.

• Journal of Information Processing Systems
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• 제12권4호
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• pp.724-740
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• 2016

The performance issues of screening large database compounds and multiple query compounds in virtual screening highlight a common concern in Chemoinformatics applications. This study investigates these problems by choosing group fusion as a pilot model and presents efficient parallel solutions in parallel platforms, specifically, the multi-core architecture of CPU and many-core architecture of graphical processing unit (GPU). A study of sequential group fusion and a proposed design of parallel CUDA group fusion are presented in this paper. The design involves solving two important stages of group fusion, namely, similarity search and fusion (MAX rule), while addressing embarrassingly parallel and parallel reduction models. The sequential, optimized sequential and parallel OpenMP of group fusion were implemented and evaluated. The outcome of the analysis from these three different design approaches influenced the design of parallel CUDA version in order to optimize and achieve high computation intensity. The proposed parallel CUDA performed better than sequential and parallel OpenMP in terms of both execution time and speedup. The parallel CUDA was 5-10x faster than sequential and parallel OpenMP as both similarity search and fusion MAX stages had been CUDA-optimized.

• 전자공학회논문지B
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• 제29B권4호
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• pp.1-11
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• 1992

트랜스퓨터를 근간으로 하는 병렬컴퓨터 "KAPAC(Kaist PArallel Computer)"을 설계하고 구현하였다. KAPAC의 목적은 복잡하거나 많은 계산이 요구되는 일을 병렬로 처리하여 속도 향상을 시킴으로써 실시간 처리및 고성능 처리를 하는 많은 응용분야에 대한 계산능력을 제공하기 위함이다. KAPAC은 UNIX 컴퓨터를 Host로 하고 VME bus에 연결할 수 있는 후위 컴퓨터로 구현하였다. 구현된 병렬 컴퓨터는 32개의 처리소자를 가지고 있는 메세지 패싱 타입의 컴퓨터이며 크로스바 스위치를 사용하여 프로그램에 의해 쉽게 연결망 형태를 구성 할 수 있도록 하였다. 구현된 병렬 컴퓨터 "KAPAC"의 재구성 특성을 보기 위하여 구성할 수 있는 다양한 연결망들을 소개했으며 몇개의 응용 프로그램들이 각기 다른 상호 연결 위상에서 수행되었다.

• 한국컴퓨터정보학회논문지
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• 제22권10호
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• pp.101-107
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• 2017

In this paper, we study the problem of parallel machine scheduling considering the moving time of multiple servers. The parallel machine scheduling is to assign jobs to parallel machines so that the total completion time(makespan) is minimized. Each job has a setup phase, a processing phase and a removal phase. A processing phase is performed by a parallel machine alone while a setup phase and a removal phase are performed by both a server and a parallel machine simultaneously. A server is needed to move to a parallel machine for a setup phase and a removal phase. But previous researches have been done under the assumption that the server moving time is zero. In this study we have proposed an efficient algorithm for the problem of parallel machine scheduling considering multiple server moving time. We also have investigated experimentally how the number of servers and the server moving time affect the total completion time.

• 제어로봇시스템학회논문지
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• 제11권1호
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• pp.84-91
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• 2005

In this paper, we describe the real-time parallel processing simulator developed for the use of performance analysis of rolling missiles. The real-time parallel processing simulator developed here consists of seeker emulator generating infrared image signal on aircraft, real-time computer, host computer, system unit, and actual equipments such as auto-pilot processor and seeker processor. Software is developed from mathematic models, 6 degree-of-freedom module, aerodynamic module which are resided in real-time computer, and graphic user interface program resided in host computer. The real-time computer consists of six TIC-40 processors connected in parallel. The seeker emulator is designed by using analog circuits coupled with mechanical equipments. The system unit provides interface function to match impedance between the components and processes very small electrical signals. Also real launch unit of missiles is interfaced to simulator through system unit. In order to apply the real-time parallel processing simulator to performance analysis equipment of rolling missiles it is essential to perform the performance verification test of simulator.

• 한국컴퓨터정보학회논문지
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• 제13권2호
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• pp.221-233
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• 2008

일반적으로 병렬처리가 필요한 경우 병렬처리 전용으로 제조된 시스템을 사용하지만, 가까운 주위에서 쉽게 얻을 수 있는 PC들을 클러스터로 구축하여 병렬처리에 활용할 수도 있다. PC들을 클러스터로 구축하기 위한 가장 쉬운 방법은 PC들을 스위치 허브 중심의 스타 네트워크로 연결하는 방법이지만, 이 논문에서는 병렬처리 연구 및 활용에 더 적합하도록 8개의 PC들이 직접 연결된 클러스터 구축을 위한 TCP/IP 기반 하이퍼큐브 네트워크의 효율적인 구현 방안을 모색하고, 그 기능 및 효율성을 ping, netperf, MPICH 등의 도구를 이용하여 검증하였다. 구현 방안으로 링크 위주의 IP 설정 방법과 노드 위주의IP 설정 방법을 제안하고 두 방법을 비교 분석하였는데, 그 결과 두 방법간에 시간적 성능 차이는 없지만 라우팅 테이블의 단순화 측면에서 노드 위주의 IP설정 방법이 우수함을 볼 수 있었다. 기능적 측면을 검증하기 위하여 응용프로그램의 병렬처리 결과를 스타 네트워크 기반클러스터에서의 결과와 비교하였는데, 두 방법 모두 완벽한 병렬처리 환경을 지원하는 것으로 나타났다.