• Proceedings of the Korean Society of Precision Engineering Conference
• /
• 2012.10a
• /
• pp.343-344
• /
• 2012

• Proceedings of the KSME Conference
• /
• 2003.11a
• /
• pp.1407-1412
• /
• 2003

In MEMS devices, packaging induced stress or stress induced structure deformation become increasing concerns since it directly affects the performance of the device. In this paper, deformation behavior of MEMS gyroscope package subjected to temparature change is investigated using high-sensitivity $Moir{\acute{e}}$ interferometry. Using the real-time $Moir{\acute{e}}$ setup, fringe patterns are recorded and analyzed at several temperatures. Temperature dependent analyses of warpages and extensions/contractions of the package are presented. Linear elastic behavior is documented in the temperature region of room temperature to $125^{\circ}C$. Analysis of the package reveals that global bending occurs due to the mismatch of thermal expansion coefficient between the chip, the molding compond and the PCB.

• Journal of the Korean Vacuum Society
• /
• v.21 no.4
• /
• pp.185-192
• /
• 2012

p-n junction temperature and thermal resistance of Light Emitting Diode (LED) package are affected by the chip size due to the change of the thermal density and the external quantum efficiency considering the heat dissipation through conduction. In this study, forward voltage was measured for two different size LED chips, 24 mil and 40 mil, which consist constitute 16-chip package. p-n junction temperature and thermal resistance were determined by thermal transient analysis, which were discussed in connection with the electrical characteristics of the LED chip and the structure of the LED package.

• Journal of the Microelectronics and Packaging Society
• /
• v.20 no.3
• /
• pp.31-35
• /
• 2013

TSOP(Thin Small Outline Package) is the IC package using lead frame, which is the type of low cost package for white electronics, auto mobile, desktop PC, and so on. Its performance is not excellent compared to BGA or flip-chip CSP, but it has been used mostly because of low price of TSOP package. However, it has been issued in TSOP package that thermal deflection of lead frame occurs frequently during molding process and Au wire between semiconductor die and pad is debonded. It has been required to solve this problem through substituting materials with low CTE and improving structure of lead frame. We focused on developing the lead frame structure having thermal stability, which was carried out by numerical analysis in this study. Thermal deflection of lead frame in TSOP package was simulated with positions of anti-deflection adhesives, which was ranging 198 um~366 um from semiconductor die. It was definitely understood that thermal deflection of TSOP package with anti-deflection adhesives was improved as 30.738 um in the case of inside(198 um), which was compared to that of the conventional TSOP package. This result is caused by that the anti-deflection adhesives is contributed to restrict thermal expansion of lead frame. Therefore, it is expected that the anti-deflection adhesives can be applied to lead frame packages and enhance their thermal deflection without any change of substitutive materials with low CTE.

• Journal of the Microelectronics and Packaging Society
• /
• v.28 no.4
• /
• pp.31-39
• /
• 2021

In this paper, warpage analysis that separates PCB for PoP (Package on Package) into unit and substrate using FEM (Finite Element Method), analysis of the effect of layer thickness on warpage, and SN (Signal-to-Noise) ratio by Taguchi method was carried. According to the analysis result, the contribution of the circuit layer on warpage was very high in the unit PCB, and the contribution of the outer layer was particularly high. On the other hand, the substrate PCB had a high influence of the circuit layer on warpage, but it was relatively low compared to the unit PCB, and the influence of the solder resist was rather increased. Therefore, considering the unit PCB and the substrate PCB at the same time, it is desirable to design the PCB for PoP layer-by-layer structure so that the outer and inner circuit layers are thick, the top solder resist is thin, and the thickness of the bottom solder resist is between 5 ㎛ and 25 ㎛.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
• /
• v.25 no.12
• /
• pp.34-41
• /
• 2011

In order to understand the thermal performance of each LED chips in multi-chip LED package, a quantitative parametric analysis of the temperature evolution was investigated by thermal transient analysis. TSP (Temperature Sensitive Parameter) value was measured and the junction temperature was predicted. Thermal resistance between the p-n junction and the ambient was obtained from the structure function with the junction temperature evolution during the cooling period of LED. The results showed that, the thermal resistance of the each LED chips in 4 chip-LED package was higher than that of single chip- LED package.

• The Journal of the Korea Contents Association
• /
• v.16 no.1
• /
• pp.42-51
• /
• 2016

For changes in the distribution structure these days, consumer demand is moving rapidly from offline to online. The consumers' mentality to purchase products conveniently is reflected in this phenomenon. Also for agricultural products, safety to protect contents, brand and design which can provide credibility to consumers are recognized as most important than ever. Especially, strawberry is thin-skinned so that the quality of product may deteriorate even with weak impact and shaking, so it is significantly influenced by the structural packaging or material. Also, strawberry is frequently distributed through direct trading, it is the reality that the package design of strawberry is less competitive than that of other products due to inadequate environments of commercial farms. That is, the demand of strawberry increases everyday but the strawberry package cannot fulfill the needs of producers and consumers. In order to reinforce competitiveness in strawberry sales, it is urgent to carry out fundamental studies regarding the development of package. Therefore, the purpose of this study is to supplement and improve issues arising from the usage of current strawberry package. Through the analysis of strawberry package elements (shape, material, design) and understand the points of improvement sought by producers and consumers through IPA MAP (importance, satisfaction level) analysis.

• The Transactions of the Korean Institute of Electrical Engineers A
• /
• v.55 no.10
• /
• pp.418-425
• /
• 2006

This paper describes a simulation package for a power system using objected-oriented programming. The package includes four parts which are a power flow, a short circuit calculation, a transient simulation program, and an economic dispatch. The graphical user interface(GUI) is designed as a common platform which allows the user to create one-line diagrams of systems, specify components of power systems as well as simulation parameters, and view the output produced by the chosen application. The paper presents the data structure of the functional modules such as the draw module, power system data module, the power system simulation module, and the utility module using the object oriented programming. This package may be useful for educational and research purposes.

• Journal of the Microelectronics and Packaging Society
• /
• v.12 no.4 s.37
• /
• pp.331-338
• /
• 2005

The rapid advances in high power light sources and arrays as encountered in incandescent lamps have induced dramatic increases in die heat flux and power consumption at all levels of high power LED packaging. The lifetime of such devices and device arrays is determined by their temperature and thermal transients controlled by the powering and cooling, because they are usually operated under rough environmental conditions. The reliability of packaged electronics strongly depends on the die attach quality, because any void or a small delamination may cause instant temperature increase in the die, leading sooner or later to failure in the operation. Die attach materials have a key role in the thermal management of high power LED packages by providing the low thermal resistance between the heat generating LED chips and the heat dissipating heat slug. In this paper, thermal transient characteristics of die attach in high power LED package have been studied based on the thermal transient analysis using the evaluation of the structure function of the heat flow path. With high power LED packages fabricated by die attach materials such as Ag paste, solder paste and Au/Sn eutectic bonding, we have demonstrated characteristics such as cross-section analysis, shear test and visual inspection after shear test of die attach and how to detect die attach failures and to measure thermal resistance values of die attach in high power LED package. From the structure function oi the thermal transient characteristics, we could know the result that die attach quality of Au/Sn eutectic bonding presented the thermal resistance of about 3.5K/W. It was much better than those of Ag paste and solder paste presented the thermal resistance of about 11.5${\~}$14.2K/W and 4.4${\~}$4.6K/W, respectively.

• Journal of the Semiconductor & Display Technology
• /
• v.17 no.4
• /
• pp.42-45
• /
• 2018

As The semiconductor decrease from 10 nanometer to 7 nanometer, It is suggested that "More than Moore" is needed to follow Moore's Law, which has been a guide for the semiconductor industry. Fan-Out Wafer Level Package(FOWLP) is considered as the key to "More than Moore" to lead the next generation in semiconductors, and the reasons are as follows. the fan-out WLP does not require a substrate, unlike conventional wire bonding and flip-chip bonding packages. As a result, the thickness of the package reduces, and the interconnection becomes shorter. It is easy to increase the number of I / Os and apply it to the multi-layered 3D package. However, FOWLP has many issues that need to be resolved in order for mass production to become feasible. One of the most critical problem is the warpage problem in a process. Due to the nature of the FOWLP structure, the RDL is wired to multiple layers. The warpage problem arises when a new RDL layer is created. It occurs because the solder ball reflow process is exposed to high temperatures for long periods of time, which may cause cracks inside the package. For this reason, we have studied warpage in the FOWLP structure using commercial simulation software through the implementation of the reflow process. Simulation was performed to reproduce the experiment of products of molding compound company. Young's modulus and poisson's ratio were found to be influenced by the order of influence of the factors affecting the distortion. We confirmed that the lower young's modulus and poisson's ratio, the lower warpage.