• 제목/요약/키워드: p-type silicon wafer

검색결과 110건 처리시간 0.029초

VVC 다이오드의 시작연구 (I) (Fabrication of Silicon Voltage Variable Capacitance Diode-(I))

  • 정만영;박계영
    • 대한전자공학회논문지
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    • 제5권3호
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    • pp.9-24
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    • 1968
  • 초단계형(Hyperabrupt) p-n접합에서 접합용량의 인가전압에 의한 변화률이 단순물분포에 따라 변화하는 성질을 이용하여 가변용량다이오드의 최적설계방법 유도하고 표준방송수신용 라디오의 동조용 가변용량실리콘 다이오드를 설계하였고 이다이오드의 제작방법에 관하여 연구하였다. 이때 도너 및 액셉터 불순물로서는 안치모니 및 알루미늅을 진공증착한 후 고온확산로에 넣어 처리하므로서 원하는 분포를 얻으려 하였다.

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Recent Development of P-Tunnel Oxide Passivated Contact Solar Cells

  • Yang Zhao;Muhammad Quddamah Khokhar;Hasnain Yousuf;Xinyi Fan;Seungyong Han;Youngkuk Kim;Suresh Kumar Dhungel;Junsin Yi
    • 한국전기전자재료학회논문지
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    • 제36권4호
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    • pp.332-340
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    • 2023
  • Crystalline silicon solar cells have attracted great attention for their various advantages, such as the availability of raw materials, high-efficiency potential, and well-established processing sequence. Tunnel oxide passivated contact (TOPCon) solar cells are widely regarded as one of the most prospective candidates for the next generation of high-performance solar cells because an efficiency of 26% has been achieved in small-area solar cells. Compared to n-type TOPCon solar cells, the photo conversion efficiency (PCE) of p-type TOPCon is slightly higher. The highest PCEs of p-type TOPCon and n-type TOPCon solar cells are 26.0% and 25.8%, respectively. Despite the highest efficiency in small-area cells, limited progress has been achieved in p-type TOPCon solar cells for large are due to their lower carrier lifetime and inferior surface passivation with the boron-doped c-Si wafer. Nevertheless, it is of great importance to promoting the p-type TOPCon technology due to its lower price and well-established manufacturing procedures with slight modifications in the PERC solar cells production lines. The progress in different approaches to increase the efficiencies of p-type TOPCon solar cells has been reported in this review article and is expected to set valuable strategies to promote the passivation technology of p-type TOPCon, which could further increase the efficiency of TOPCon solar cells.

$CO_2$ Laser-induced CVD법에 의한 Silicon박막 및 p-n 접합 Silicon제작 (Silicon thin film and p-n junction diode made by $CO_2$ laser-induced CVD method)

  • 최원국;정광호;김웅
    • 대한전기학회:학술대회논문집
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    • 대한전기학회 1989년도 하계종합학술대회 논문집
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    • pp.662-666
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    • 1989
  • Pure mono Silane(Purity: 99.99%) was used as a thin film source and [$SiH_4$ + $H_2$ (5%)] + [$PH_3$ + $H_2$(0.05%)] mixed dilute gas was used for p-n junction diode. The substrate was P-type silicon wafer (p=$3{\Omega}$ cm) with the direction (100). The crystalline qualities of deposited thin film were investigated by the X-ray diffraction, RHEED and TED patterns and the voltampere characteristics of p-n junction diode was identified by I-V curve.

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웨이퍼 본딩을 이용한 탐침형 정보 저장장치용 열-압전 켄틸레버 어레이 (Thermo-piezoelectric $Si_3N_4$ cantilever array on n CMOS circuit for probe-based data storage using wafer-level transfer method)

  • 김영식;장성수;이선영;진원혁;조일주;남효진;부종욱
    • 정보저장시스템학회:학술대회논문집
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    • 정보저장시스템학회 2005년도 추계학술대회 논문집
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    • pp.22-25
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    • 2005
  • In this research, a wafar-level transfer method of cantilever array on a conventional CMOS circuit has been developed for high density probe-based data storage. The transferred cantilevers were silicon nitride ($Si_3N_4$) cantilevers integrated with poly silicon heaters and piezoelectric sensors, called thermo-piezoelectric $Si_3N_4$ cantilevers. In this process, we did not use a SOI wafer but a conventional p-type wafer for the fabrication of the thermo-piezoelectric $Si_3N_4$ cantilever arrays. Furthermore, we have developed a very simple transfer process, requiring only one step of cantilever transfer process for the integration of the CMOS wafer and cantilevers. Using this process, we have fabricated a single thermo-piezoelectric $Si_3N_4$ cantilever, and recorded 65nm data bits on a PMMA film and confirmed a charge signal at 5nm of cantilever deflection. And we have successfully applied this method to transfer 34 by 34 thermo-piezoelectric $Si_3N_4$ cantilever arrays on a CMOS wafer. We obtained reading signals from one of the cantilevers.

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Pore Distribution of Porous Silicon layer by Anodization Process

  • Lee, Ki-Yong;Chung, Won-Yong;Kim, Do-Hyun
    • 한국결정성장학회:학술대회논문집
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    • 한국결정성장학회 1996년도 The 9th KACG Technical Annual Meeting and the 3rd Korea-Japan EMGS (Electronic Materials Growth Symposium)
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    • pp.494-496
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    • 1996
  • The purpose of this study is to investigate the effect of process conditions on pore distribution in porous silicon layer prepared by electrochemical reaction. Porous silicon layers formed on p-type silicon wafer show the network structure of fine porse whose diameters are less than 100${\AA}$. In n-type porous silicon, selective growth was found on the pore surface by wet etching process after PR patterning. And numerical method showed high current density on the pore tip. With this result we confirmed that pore formation has two steps. First step is the initial attack on the surface and second step is the directional growth on the pore tip.

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실리콘 이종접합 태양전지에서 계면 결함 밀도의 영향 (Influence of the interface defect density on silicon heterojunction solar cells)

  • 김찬석;이승훈;탁성주;최수영;부현필;이정철;김동환
    • 한국신재생에너지학회:학술대회논문집
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    • 한국신재생에너지학회 2011년도 춘계학술대회 초록집
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    • pp.103.1-103.1
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    • 2011
  • 실리콘 이종접합 태양전지에서 계면 결함 밀도는 효율을 결정하는데 가장 중요한 요인으로 작용한다. 계면 결함은 캐리어의 재결합 위치로 작용하여, 계면 결함 밀도가 증가하면 재결합 속도가 증가하게 된다. 흡수층으로 사용되는 실리콘 웨이퍼 (결정질 실리콘)를 가능한 깨끗하게 세정함으로써, 또한 emitter로 쓰이는 비정질 실리콘을 낮은 데미지로 증착하여 계면 결함 밀도를 감소 시킬 수 있다. 이러한 계면 결함 밀도의 감소가 어떠한 변화로 인해 태양전지 특성에 영향을 주는지 시물레이션을 통해 알아보았다. n-type 웨이퍼에 p-type 비정질 실리콘을 emitter로 하여 TCO/p/i/n-type wafer/i/n/TCO/metal의 구조를 적용했고, wafer 전면과 i로 쓰인 무첨가된 비정질 실리콘 간의 계면 결함 밀도를 변수로 적용했다. 그 결과, 계면 결함 밀도가 감소함에 따라 재결합이 감소하여 태양전지 특성이 증가하는 측면도 있지만, 흡수층의 장벽 (barrier height)이 높아져 재결합을 더욱 감소시킴으로 인해 태양전지 특성이 증가함을 알 수 있었다.

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Dislocations as native nanostructures - electronic properties

  • Reiche, Manfred;Kittler, Martin;Uebensee, Hartmut;Pippel, Eckhard;Hopfe, Sigrid
    • Advances in nano research
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    • 제2권1호
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    • pp.1-14
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    • 2014
  • Dislocations are basic crystal defects and represent one-dimensional native nanostructures embedded in a perfect crystalline matrix. Their structure is predefined by crystal symmetry. Two-dimensional, self-organized arrays of such nanostructures are realized reproducibly using specific preparation conditions (semiconductor wafer direct bonding). This technique allows separating dislocations up to a few hundred nanometers which enables electrical measurements of only a few, or, in the ideal case, of an individual dislocation. Electrical properties of dislocations in silicon were measured using MOSFETs as test structures. It is shown that an increase of the drain current results for nMOSFETs which is caused by a high concentration of electrons on dislocations in p-type material. The number of electrons on a dislocation is estimated from device simulations. This leads to the conclusion that metallic-like conduction exists along dislocations in this material caused by a one-dimensional carrier confinement. On the other hand, measurements of pMOSFETs prepared in n-type silicon proved the dominant transport of holes along dislocations. The experimentally measured increase of the drain current, however, is here not only caused by an higher hole concentration on these defects but also by an increasing hole mobility along dislocations. All the data proved for the first time the ambipolar behavior of dislocations in silicon. Dislocations in p-type Si form efficient one-dimensional channels for electrons, while dislocations in n-type material cause one-dimensional channels for holes.

N-Type c-Si 이종접합 태양전지 제작을 위한 a-Si:H(p) 가변 최적화 (A Study of Optimization a-Si:H(p) for n-type c-Si Heterojunction Solar Cell)

  • 허종규;윤기찬;최형욱;이영석;;김영국;이준신
    • 한국신재생에너지학회:학술대회논문집
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    • 한국신재생에너지학회 2009년도 춘계학술대회 논문집
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    • pp.77-79
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    • 2009
  • Amorphous/crystalline silicon heterojunction solar cells, TCO/a-Si:H (p)/c-Si(n)/a-Si:H(n)/Al, are investigated. The influence of various parameters for the front structures was studied. We used thin (10 nm) a-Si:H(p) layers of amorphous hydrogenated silicon are deposited on top of a thick ($500{\mu}m$) crystalline c-Si wafer. This work deals with the influence of the a-Si:H(p) doping concentration on the solar cell performance is studied.

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Chemical Sensors Based on Distributed Bragg Reflector Porous Silicon Smart Particles

  • Sohn, Honglae
    • 통합자연과학논문집
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    • 제8권1호
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    • pp.67-74
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    • 2015
  • Sensing characteristics for porous smart particle based on DBR smart particles were reported. Optically encoded porous silicon smart particles were successfully fabricated from the free-standing porous silicon thin films using ultrasono-method. DBR PSi was prepared by an electrochemical etch of heavily doped $p^{++}$-type silicon wafer. DBR PSi was prepared by using a periodic pseudo-square wave current. The surface-modified DBR PSi was prepared by either thermal oxidation or thermal hydrosilylation. Free-standing DBR PSi films were generated by lift-off from the silicon wafer substrate using an electropolishing current. Free-standing DBR PSi films were ultrasonicated to create DBR-structured porous smart particles. Three different surface-modified DBR smart particles have been prepared and used for sensing volatile organic vapors. For different types of surface-modified DBR smart particles, the shift of reflectivity mainly depends on the vapor pressure of analyte even though the surfaces of DBR smart particles are different. However huge difference in the shift of reflectivity depending on the different types of surface-modified DBR smart particles was obtained when the vapor pressures are quite similar which demonstrate a possible sensing application to specify the volatile organic vapors.

Improved Rs Monitoring for Robust Process Control of High Energy Well Implants

  • Kim, J.H.;Kim, S.;Ra, G.J.;Reece, R.N.;Bae, S.Y.
    • 한국반도체및디스플레이장비학회:학술대회논문집
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    • 한국반도체및디스플레이장비학회 2007년도 춘계학술대회
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    • pp.109-112
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    • 2007
  • In this paper we describe a robust method of improving precision in monitoring high energy ion implantation processes. Ion implant energy accuracy was measured in the device manufacturing process using an unpatterned implanted layer on an intrinsic p-type silicon wafer. To increase Rs sensitivity to energy at the well implant process, a PN junction structure was formed by P-well and deep N-well implants into the p-type Si wafer. It was observed that the depletion layer formed by the PN junction was very sensitive to energy variation of the well implant. Conclusively, it can be recommended to monitor well implant processes using the Rs measurement method described herein, i.e., a PN junction diode structure since it shows excellent Rs sensitivity to variation caused by energy difference at the well implant step.

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