• JSTS:Journal of Semiconductor Technology and Science
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• v.6 no.1
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• pp.16-21
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• 2006

A simple doping method to fabricate a very thin channel body of the p-type FinFETs with a 20 nm gate length by solid-phase-diffusion (SPD) process was developed. Using the poly-boron-films (PBF) as a novel diffusion source of boron and the rapid thermal annealing (RTA), the p-type sourcedrain extensions of the FinFET devices with a threedimensional structure were doped. The junction properties of boron doped regions were investigated by using the $p^+-n$ junction diodes which showed excellent electrical characteristics. Single channel and multi-channel p-type FinFET devices with a gate length of 20-100 nm was fabricated by boron diffusion process using PBF and revealed superior device scalability.

• Journal of the Korean Vacuum Society
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• v.16 no.6
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• pp.414-423
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• 2007

Field Emission Display(FED) has significant advantages over existing display technologies, particularly in the area of small and high quality display. In order to test the feasibility of fabricating the System-on-Chip(SOC) with FED, we conducted the experiment to use the p-n junction as an electron beam source for the flat panel display. A novel structure was constructed to form p-n junctions by generating inversion layer with the electric field from the cantilever style gate. When we applied more than 220V at the cantilever style gate which has a height of $1{\mu}m$, avalanche breakdown onset was successfully achieved. The characteristics was compared with the electron emission from the ultra shallow junction in the avalanche region. The experiment result and the future direction were discussed.

• Proceedings of the IEEK Conference
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• 2000.06b
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• pp.270-273
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• 2000

We have fabricated and analyzed photodiodes for optical link with Si pin structures. As the results of experiment, the web patterned photodiode(type C) with $p^{+}$-guard ring showed low junction capacitance of 6~7 pF at $V_{R}$=-5V and high separation ability for optical signal(dark current : $\leq$ 5 nA, optical signal current : $\geq$ 340 nA) due to the small effective $p^{+}$-n junction area and the expanded electric field region. The fabricated Si pin photodiode can be applicable for detecting an optical signal with the wavelength of about 660~670 nm. It can also be integrated with the twin well CMOS structure to develope an one chip based optical receiver IC. IC.C.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.06a
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• pp.146-147
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• 2009

$CuGaSe_2$ (CGS) layers were grown by the hot wall epitaxy method. The optimum temperatures of the substrate and source for growth turned out to be 450 and $610^{\circ}C$, respectively. Based on the absorption measurement, the band-gap variation of CGS was well interpreted by the Varshni's equation. By analyzing these emissions, a band diagram of the observed optical transitions was obtained. From the solar cell measurement, an 11.17 % efficiency on the n-CdS/p-CGS junction was achieved.

• JSTS:Journal of Semiconductor Technology and Science
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• v.6 no.1
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• pp.43-51
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• 2006

80-nm self-aligned n-and p-channel I-MOS devices were demonstrated by using a novel fabrication method featuring double sidewall spacer, elevated drain structure and RTA process. The fabricated devices showed a normal transistor operation with extremely small subthreshold swing less than 12.2 mV/dec at room temperature. The n- and p-channel I-MOS devices had an ON/OFF current of 394.1/0.3 ${\mu}A$ and 355.4/8.9 ${\mu}A$ per ${\mu}m$, respectively. We also investigated some critical issues in device design such as the junction depth of the source extension region and the substrate doping concentration.

• The Transactions of the Korean Institute of Electrical Engineers
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• v.45 no.3
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• pp.386-392
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• 1996

Zinc-Borosilicate is used as a side insulator wall to make high breakdown voltage with one Field Limiting Ring in a power p-n junction device in simulation. It is known that surface charge density can be yield at the interface of Zinc-Borosilicate glass / silicon system. When the glass is used as a side insulator wall, surface charge varied potential distribution and breakdown voltage is improved 1090 V under the same structure.The breakdown voltage under varying the surface charge density has a limit value. When the epitaxial thickness is varied, the position of FLR doesn't influence to the breakdown characteristic not only under non punch-through structure but also under punch-through structure. (author). 7 refs., 12 figs., 2 tabs.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.35D no.12
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• pp.53-58
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• 1998

A buried channel poly-Si TFT (BCTFT) for application of high performance integrated circuits has been proposed and fabricated. BCTFT has unique features, such as the moderately-doped buried channel and counter-doped body region for conductivity modulation, and the fourth terminal entitled back bias for preventing kink effect. The n-type and p-type BCTFT exhibits superior performance to conventional poly-Si TFT in ON-current and field effect mobility due to moderate doping at the buried channel. The OFF-state leakage current is not increased because the carrier drift is suppressed by the p-n junction depletion between the moderately-doped buried channel and the counter-doped body region.

• Journal of the Semiconductor & Display Technology
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• v.16 no.2
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• pp.39-43
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• 2017

It was confirmed that the silicon thin films fabricated on the p-Si (100) substrates by using DIPAS (DiIsoPropylAminoSilane) and TDMA-Sb (Tris-DiMethylAminoAntimony) sources by RPCVD method were amorphous and n-type silicon. The fabricated amorphous n-type silicon films had electron carrier concentrations and electron mobilities ranged from $6.83{\times}10^{18}cm^{-3}$ to $1.27{\times}10^{19}cm^{-3}$ and from 62 to $89cm^2/V{\cdot}s$, respectively. The ideality factor of the pn junction diode fabricated on the p-Si (100) substrate was about 1.19 and the efficiency of the fabricated pn solar cell was 10.87%.

• Journal of Sensor Science and Technology
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• v.16 no.4
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• pp.259-262
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• 2007

This paper describes the electrical characteristics of polycrystalline (poly) 3C-SiC thin film diodes, in which poly 3C-SiC thin films on n-type and p-type Si wafers, respectively, were deposited by APCVD using HMDS, $H_{2}$, and Ar gas at $1150^{\circ}C$ for 3 hr. The schottky diode with Au/poly 3C-SiC/Si (n-type) structure was fabricated. Its threshold voltage ($V_{bi}$), breakdown voltage, thickness of depletion layer, and doping concentration ($N_{D}$) value were measured as 0.84 V, over 140 V, 61 nm, and $2.7{\times}10^{19}cm^{-3}$, respectively. Moreover, for the good ohmic contact, Al/poly 3C-SiC/Si (n-type) structure was annealed at 300, 400, and $500^{\circ}C$, respectively for 30 min under the vacuum condition of $5.0{\times}10^{-6}$ Torr. Finally, the p-n junction diodes fabricated on the poly 3C-Si/Si (p-type) were obtained like characteristics of single 3CSiC p-n junction diode. Therefore, poly 3C-SiC thin film diodes will be suitable for microsensors in conjunction with Si fabrication technology.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.20 no.5
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• pp.394-398
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• 2007

A simple doping method to fabricate a very thin channel body of the nano-scaled n-type fin field-effect-transistor (FinFET) by arsenic solid-Phase-diffusion (SPD) process is presented. Using the As-doped spin-on-glass films and the rapid thermal annealing for shallow junction, the n-type source-drain extensions with a three-dimensional structure of the FinFET devices were doped. The junction properties of arsenic doped regions were investigated by using the $n^+$-p junction diodes which showed excellent electrical characteristics. The n-type FinFET devices with a gate length of 20-100 nm were fabricated by As-SPD and revealed superior device scalability.