• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2003년도 하계학술대회 논문집 Vol.4 No.2
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• pp.864-867
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• 2003

Since the development of semiconductors, various related research has been conducted. During research, silicon diodes have been commonly used because of their simplicity and low cost in the manufacturing process. This research deals with p-n junction threshold voltages from silicon diodes due to transport current at a cryogenic temperature. At a cryogenic temperature(77K) we could get minimum current which junction threshold voltage becomes constant. This is experimented on GPIB communication and it consist of programmable current source, multimeter which gauge the threshold voltage in a very low temperature caused by transport current from 5nA to 1mA and $LN_2$(77K) for coolant. This experiment is programmed all process using Measurement studio(Lab window) tool.

• 한국진공학회지
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• 제19권5호
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• pp.391-396
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• 2010

실리콘 태양전지의 pn 접합 계면특성을 조사하기 위해서 p형 실리콘 기판 위에 전기로를 이용한 $POCl_3$ 공정을 통하여 n형의 불순물을 주입하여 pn 접합을 만들었다. n형 불순물의 확산되어 들어가는 공정시간이 길고 공정온도가 높을수록 면저항은 줄어들었다. n형 불순물의 주입이 많아질수록 pn 접합 계면에서의 전자친화도가 줄어들면서 면저항은 감소되었다. 면저항이 줄어든 이유는 pn 접합계면에서 전자홀쌍이 생성되면서 이동길이가 길어지고 재결합률이 감소하였기 때문이다. n형의 불순물 확산공정시간이 긴 태양전지 셀에서 F.F. 계수가 높게 나타났으며, 효율도 높게 나타났다.

• 전자공학회논문지A
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• 제31A권8호
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• pp.80-90
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• 1994

The ultra shallow junction was formed by 2-step RTP. Phosphorus solid source(P$_{2}O_{5}$) was transfered on wafer surface during RTG(Rapid Thermal Glass Transfer) of which process condition was 80$0^{\circ}C$ and 60sec. The process temperature and time of the RTD(Rapid Thermal Diffusion) were 950~105$0^{\circ}C$ during 5~15sec respectively sheet resistances were measured as 175~320$\Omega$/m and junction depth and dopth and dopant surface concentration were measured as 0.075~0.18$\mu$m and 5${\times}10^{19}cm^{4}$ respectively. Ti-silicide was formed by 2-step RTA after 300$\AA$ Titanium was deposited. The 1st RTA (2nd RTA) was carried out at the temperature of $600^{\circ}C$(700~80$0^{\circ}C$) for 30 seconds (10~60 seconds) under N$_2$ ambient. Sheet resistances after 2nd RTA were measured as 46~63$\Omega$/D. Si/Ti component ratio was evaulated as 1.6~1.9 from Auger depth profile. Ti-Silicided n-p junction diode (pattern size : 400$\times$400$\mu$m) was fabricated under the RTD(the process was carried out at the temperature of 100$0^{\circ}C$ for 10seconds) and 2nd RTA(theprocess was carried out at the temperature of 750$^{\circ}C$ for 60 seconds). Leakage current was measured 1.8${\times}10^{7}A/mm^{2}$ at 5V reverse voltage. Whent the RTD process condition is at the temperature of 100$0^{\circ}C$ for 10seconds and the 2nd RTA process condition is at the temperature of 75$0^{\circ}C$ for 60 seconds leakage current was 29.15${\times}10^{9}A$(at 5V).

• 한국전기전자재료학회논문지
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• 제33권3호
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• pp.173-176
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• 2020

This study focuses on a pillar in which is implanted a P-type maneuver under a P base. This structure is called a super junction structure. By inserting the pillar, the electric field concentrated on the P base is shared by the pillar, so the columns can be dispersed while maintaining a high breakdown voltage. Ten pillars were generated during the multi epitaxial process. The interval between pillars is varied to optimize the electric field to be concentrated on the pillar at a threshold voltage of 6 V, a yield voltage of 4,500 V, and an on-state voltage drop of 3.8 V. The density of the filler gradually decreased when the interval was extended by implanting a filler with the same density. The results confirmed that the size of the depletion layer between the filler and the N-epitaxy layer was reduced, and the current flowing along the N-epitaxy layer was increased. As the interval between the fillers decreased, the cost of the epitaxial process also decreased. However, it is possible to confirm the trade-off relationship that deteriorated the electrical characteristics and efficiency.

• 한국전기전자재료학회논문지
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• 제13권11호
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• pp.908-913
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• 2000

CoSi$_2$/p+/n diodes(bilayer diodes) were fabricated by using epitaxial CoSi$_2$grown from Co/Ti bilayer as a diffusion source. The I-V characteristics of p+/n diodes were measured and compared with those of diode made from Co monolayer (monolayer diode). Monolayer diodes showed typical p+n junction characteristics with the leakage current of as low as 10$^{-12}$ A and forward current 6-orders higher than the leakage current, when drive-in annealed at 90$0^{\circ}C$ for 20 sec.. On the other hand, bilayer diodes showed the Schottky-like behaviors with forward currents rather higher than those of monolyer diodes, but with too high leakage currents, when drive-in annealed at $700^{\circ}C$ or higher. However, when the annealing temperature was lowered to $700^{\circ}C$ and annealing time was increased to 60 sec., the leakage current was reduced to 10$^{-11}$ A and thus sho3wed typical diode characteristics. The high leakage currents for diodes annealed at $700^{\circ}C$ or higher was attributed to Shannon contacts formed due to unremoved Co-Ti-Si precipitates. But when annealed at 50$0^{\circ}C$, B ions diffused in the direction of the surface layer, and thus the leakage currents were reduced by removing Shannon contacts.

• 센서학회지
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• 제23권3호
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• pp.185-191
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• 2014

The width of depletion region in a varactor diode can be modulated by varying a reverse bias voltage. Thus, the preferred characteristics of depletion capacitance can obtained by the change in the width of depletion region so that it can select only the desirable frequencies. In this paper, the TV tuner varactor diode fabricated by hyper-abrupt profile control technique is presented. This diode can be operated within 3.3 V of driving voltage with capability of UHF band tuning. To form the hyperabrupt profile, firstly, p+ high concentration shallow junction with $0.2{\mu}m$ of junction depth and $1E+20ions/cm^3$ of surface concentration was formed using $BF_2$ implantation source. Simulation results optimized important factors such as epitaxial thickness and dose quality, diffusion time of n+ layer. To form steep hyper-abrupt profile, Formed n+ profile implanted the $PH_3$ source at Si(100) n-type epitaxial layer that has resistivity of $1.4{\Omega}cm$ and thickness of $2.4{\mu}m$ using p+ high concentration Shallow junction. Aluminum containing to 1% of Si was used as a electrode metal. Area of electrode was $30,200{\mu}m^2$. The C-V and Q-V electric characteristics were investigated by using impedance Analyzer (HP4291B). By controlling of concentration profile by n+ dosage at p+ high concentration shallow junction, the device with maximum $L_F$ at -1.5 V and 21.5~3.47 pF at 0.3~3.3 V was fabricated. We got the appropriate device in driving voltage 3.3 V having hyper-abrupt junction that profile order (m factor) is about -3/2. The deviation of capacitance by hyper-abrupt junction with C0.3 V of initial capacitance is due to the deviation of thermal process, ion implantation and diffusion. The deviation of initial capacitance at 0.3 V can be reduced by control of thermal process tolerance using RTP on wafer.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2004년도 춘계학술대회 논문집 반도체 재료 센서 박막재료 전자세라믹스
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• pp.30-33
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• 2004

Shallow p+-n junctions were formed by low-energy ion implantation and dual-step annealing processes The dopant implantation was performed into the crystalline substrates using $BF_2$ ions. The annealing was performed with a rapid thermal processor and a furnace. FA+RTA annealing sequence exhibited better junction characteristics than RTA+FA thermal cycle from the viewpoint of junction depth. A new simulator is designed to model boron diffusion in silicon, which is especially useful for analyzing the annealing process subsequent to ion implantation. The model which is used in this simulator takes into account nonequilibrium diffusion, reactions of point defects, and defect-dopant pairs considering their charge states, and the dopant inactivation by introducing a boron clustering reaction. Using a resonable parameter values, the simulator covers not only the equilibrium diffusion conditions but also the nonequilibrium post-implantation diffusion. Using initial conditions and boundary conditions, coupled diffusion equation is solved successfully. The simulator reproduced experimental data successfully.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2008년도 하계학술대회 논문집 Vol.9
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• pp.178-178
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• 2008

초소형 박막의 열전 발전모듈은 작은 부피와 한번 설치시 교체없이 지속적인 전원공급으로 소형의 센서 노드에 전원으로 각광 받고 있다. 이에 본 논문에서는 In Plane방식의 PIN Junction의 박막형 열전소자를 제작하여 보았다. 열전 박막인 P-type의 $BiSbTe_3$와 N-type의 $Bi_2Te_3$은 (001)GaAs 기판에 MOCVD(Metal Organic Chemical Vapour Deposition)방식으로 성장하였으며 전극으로는 E-Beam Evaporator를 이용하여 금(Au), 알루미늄(Al)을 사용하였다. 열전박막의 두께는 MOCVD의 성장시간과 온도 MO-x 가스의 압력으로 조절하여 주었다. 제작결과 1Pairs 당 약 $63{\mu}V$/K을 나타내었다.

• 대한전자공학회논문지
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• 제21권1호
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• pp.62-70
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• 1984

비저항이 10Ω-cm, 두께가 13∼15mi1인 <111> oriented, p형 Si기판을 이용하여 N+PP+ BSF 전지와 에미터 영역이 N+N 고저 접합으로 이루어진 N+NPP+ HELEBSF(high low emitter bach surface field) 전지를 설계 제작하였다. 접합형 태양전지의 에미터 영역에서 고저 접합구조가 효율 개선에 미치는 영향을 검토하기 위해 HLEBSF 전지의 N영역을 제외하고는 같은 마스크와 동시 공정을 통해 N+PP-전지와 N+NPP+ 전지의 가영역에서 물리적 파라미터들(불순물 농도, 두께)을 동일하게 만들었다. 100mW/㎠의 인공조명에서 측정한 결과 N+PP+ 전지들의 전면적 (유효 수광면적) 평균 변환효율이 10.94%(12.16%)이었고, N+NPP+ 전지들의 평균 변환효율은 12.07% (13.41%)로 나타났다. N+NPP+ 전지의 효율개선은 N+N-고저 접합 에미터 구조가 N+ 에미터 영역에서 나타나는 heavy doping effects를 제거함으로써 에미터 재결합 전류의 증가를 억제하고 나아가 개방전압(Voc)과 단락전류(Ish)의 값을 증가시켜 준 결과로 볼 수 있다.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1991년도 추계학술대회 논문집 학회본부
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• pp.286-289
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• 1991

We simulated ion implantation and annealing condition of 1 ${\mu}m$ CMOS device using process simulator, SUPREM-II. In this simulation, optimal condition of ion implantation for symmetric threshold voltage determination of PMOS and NMOS region, junction depth and sheet resistance of source/drain region, impurity profile of each region are investigated. Ion implantation dose for 3 ${\mu}m$ N-well junction depth and symmetric threshold voltage of $|0.6|{\pm}0.1$ V were $1.9E12Cm^{-2}$(for phosphorus), $1.7E122Cm^{-2}$(for boron) respectively. Also annealing condition for dopant activation are examined about $900^{\circ}C$, 30 minutes. After final process step, N-well junction, P+ S/D junction and N+ S/D junction depth are calculated 3.16 ${\mu}m$, 0.45 ${\mu}m$ and 0.25 ${\mu}m$ respectively.