• Korean Journal of Materials Research
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• v.15 no.6
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• pp.413-418
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• 2005

Perovskite $Pb(Ni_{1/3}Nb_{2/3})O_3-Pb(Zr,Ti)O_3[PNN-PZT]$ ceramics were synthesized by conventional ceramic processing technique. In order to modify piezoelectric properties for sensor application in this system, NiO addition was considered to provide $Ni^{+2}$ as an acceptor, which was known to occupy with B site in the structure. The effect of NiO addition up to $8\;mol\%$ on the following piezoelectric properties as well as sintering properties was investigated. When NiO added more than $1\;mol\%$, average grain size was decreased and second phase was found to form. Moreover, the second phase caused decrease in relative dielectric constant $(\varepsilon_{33}T/\varepsilon0)$, electro-mechanical coupling factor $(k_p)$, and piezoelectric charge constant $(d_{33})$, while increasing mechanical quality factor $(Q_m)$. When $1\;mol\%$ NiO was added, density, dielectric properties and piezoelectric properties were abruptly increased.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.21 no.4
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• pp.596-601
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• 2020

Silicon carbide is considered a potentially useful material for high-temperature electronic devices because of its large band gap energy and p-type or n-type conduction that can be controlled by impurity doping. Accordingly, the thermoelectric properties of -SiC powder prepared by refined diatomite were investigated for high value-added applications of natural diatomite. -SiC powder was synthesized by a carbothermal reduction of the SiO₂ in refined diatomite using carbon black. An acid-treatment process was then performed to eliminate the remaining impurities (Fe, Ca, etc.). n-Type semiconductors were fabricated by sintering the pressed powder at 2000℃ for 1~5h in an N2 atmosphere. The electrical conductivity increased with increasing sintering time, which might be due to an increase in carrier concentration and improvement in grain-to-grain connectivity. The carrier compensation effect caused by the remaining acceptor impurities (Al, etc.) in the obtained -SiC had a deleterious influence on the electrical conductivity. The absolute value of the Seebeck coefficient increased with increasing sintering time, which might be due to a decrease in the stacking fault density accompanied by grain or crystallite growth. On the other hand, the power factor, which reflects the thermoelectric conversion efficiency of the present work, was slightly lower than that of the porous SiC semiconductors fabricated by conventional high-purity -SiC powder, it can be stated that the thermoelectric properties could be improved further by precise control of an acid-treatment process.

• Journal of the Korean Chemical Society
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• v.50 no.4
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• pp.315-320
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• 2006

manganese oxides have been prepared by Chimie Douce redox reaction between permanganate and chalcogen element fine powder under acidic condition (pH = 1). According to powder X-ray diffraction analyses, the S- and Se-doped manganese oxides are crystallized with layered birnessite and tunnel-type -MnO2 structures, respectively. On the contrary, Te-doped compound was found to be X-ray amorphous. According to EDS analyses, these compounds contain chalcogen dopants with the ratio of chalcogen/manganese = 4-7%. We have investigated the chemical bonding character of these materials with X-ray absorption spectroscopic (XAS) analysis. Mn K-edge XAS results clearly demonstrated that the manganese ions are stabilized in octahedral symmetry with the mixed oxidation states of +3/+4. On the other hand, according to Se K- and Te L1-edge XAS results, selenium and tellurium elements have the high oxidation states of +6, which is surely due to the oxidation of neutral chalcogen element by the strong oxidant permanganate ion. Taking into account their crystal structures and Mn oxidation states, the obtained manganese oxides are expected to be applicable as electrode materials for lithium secondary batteries.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2007.11a
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• pp.279-279
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• 2007

비휘발성 메모리 Fe-RAM은 빠른 정보처리 속도와 전원공급이 차단되었을 때도 계속 정보를 유지할 수 있는 비휘발성 특징과 더불어 저전압, 저전력 구동의 장점이 있어서, 차세대 메모리로 많은 주목을 받고 있다. FeRAM에 사용되는 강유전체는 주로 Pb(Zr,Ti)$O_3$가 적용되었는데, 최근에는 비납계 강유전체의 연구도 활발히 이루어지고 있다. 이러한 비납계 강유전체 중에서 가장 특성이 우수한 물질은 $(Bi,La)_4Ti_3O_{12}$ (BLT) 이다. 그런데 BLT는 결정 방향에 따른 강한 이방성의 강유전 특성을 나타내기 때문에 BLT 박막을 이용하여 Fe-RAM 소자 등을 제작하기 위해서는 결정의 방향성을 세심하게 제어하는 것이 매우 중요하다. 지금까지 연구된 BLT 박막의 방향성 조절결과를 보면, BLT 박막을 스핀 코팅 법 (spin coating method)으로 증착하고, 핵생성 열처리 단계를 조절하여 무작위 방향성을 갖는 박막을 제조하는 방법이 일반적이었다. 그런데 이러한 스핀 코팅법에서의 핵생성 단계의 제어는 공정 조건 확보가 너무 어려운 단점이 있다. 이러한 어려움을 극복할 수 있는 대안은 스퍼터링 증착법(sputtering deposition method), PLD (pulsed laser deposition)법 등과 같은 PVD (physical vapor deposition) 법의 증착방법을 적용하는 것이다. PVD 법으로 증착하는 경우에는 이미 박막 내에 무수한 결정핵이 존재하기 때문에 핵생성 단계가 필요가 없게 된다. PVD 증착법의 적용을 위해서는 타겟의 제조 및 평가 실험이 선행되어야 한다. 그런데 벌크 BLT 재료의 소결공정 조건과 전기적 특성에 관한 연구 결과는 거의 발표가 되지 않고 있다. 본 실험에서는 $Bi_2O_3,\;TiO_2,\;La_2O_3,\;Nb_2O_5\;and\;Al_2O_3$ 분말들을 이용하여 최적의 조성을 구하기 위하여 $Nb^{+5}$ 와 $Al^{+3}$을 $Ti^{+4}$ 자리에 소량 치환시켜 제조하였다. 혼합된 분말을 하소 후 pellet 형태로 성형하여 소결을 실시하였다. 시편을 1mm 두께로 연마하고, 양면에 silver 전극을 인쇄하여 전기적 특성을 측정하였다. 측정결과 $Ti^{+4}$ 자리에 $Nb^{+5}$를 치환하여 제조한 시편에서 $2P_r{\sim}31\;{\mu}c/cm^2$정도의 매우 우수한 특성을 얻었다.

• Membrane Journal
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• v.25 no.5
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• pp.415-421
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• 2015

$SrCo_{0.8}Fe_{0.1}Nb_{0.1}O_{3-{\delta}}$ oxide was synthesized by solid state reaction method. Dense ceramic membrane was prepared using as-prepared powder by pressing and sintering at $1250^{\circ}C$. XRD result of membrane showed single perovskite structure. The oxygen permeability were measured under 0.21 atm of oxygen partial pressure ($P_{O_2}$) and between 800 and $950^{\circ}C$. The oxygen permeation flux of $SrCo_{0.8}Fe_{0.1}Nb_{0.1}O_{3-{\delta}}$ membrane was increased with the increasing temperature. The maximum oxygen permeation flux was $1.839mL/min{\cdot}cm^2$ at $950^{\circ}C$. Long period permeability experiment was carried out to confirm the phase stability and $CO_2$-tolerance of membrane containing Nb in the condition of air with $CO_2$ (500 ppm) as feed stream at $900^{\circ}C$. The phase stability and $CO_2$-tolerance of $SrCo_{0.8}Fe_{0.1}Nb_{0.1}O_{3-{\delta}}$ were investigated by XRD and TG analysis. The result of $SrCo_{0.8}Fe_{0.1}Nb_{0.1}O_{3-{\delta}}$ which exposed carbon dioxide for 100 hours indicated 8wt% of $SrCO_3$. But it was known that the level of $SrCO_3$ production dose not have a significant effect on oxygen permeability.

• Proceedings of the Korean Vacuum Society Conference
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• 2010.02a
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• pp.456-456
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• 2010

CMOS 소자가 서브마이크론($0.1\;{\mu}m$) 이하로 스케일다운 되면서 단채널 효과(short channel effect), 게이트 산화막(gate oxide)의 누설전류(leakage current)의 증가와 높은 직렬저항(series resistance) 등의 문제가 발생한다. CMOS 소자의 구동전류(drive current)를 높이고, 단채널 효과를 줄이기 위한 가장 효율적인 방법은 소스 및 드레인의 얕은 접합(shallow junction) 형성과 직렬 저항을 줄이는 것이다. 플라즈마 도핑 방법은 플라즈마 밀도 컨트롤, 주입 바이어스 전압 조절 등을 통해 저 에너지 이온주입법보다 기판 손상 및 표면 결함의 생성을 억제하면서 고농도로 얕은 접합을 형성할 수 있다. 그리고 얕은 접합을 형성하기 위해 주입된 불순물의 활성화와 확산을 위해 후속 열처리 공정은 높은 온도에서 짧은 시간 열처리하여 불순물 물질의 활성화를 높여주면서 열처리로 인한 접합 깊이를 얕게 해야 한다. 그러나 접합의 깊이가 줄어듦에 따라서 소스 및 드레인의 표면 저항(sheet resistance)과 접촉저항(contact resistance)이 급격하게 증가하는 문제점이 있다. 이러한 표면저항과 접촉저항을 줄이기 위한 방안으로 실리사이드 박막(silicide thin film)을 형성하는 방법이 사용되고 있다. 본 논문에서는 (100) p-type 웨이퍼 He(90 %) 가스로 희석된 $PH_3$(10 %) 가스를 사용하여 플라즈마 도핑을 실시하였다. 10 mTorr의 압력에서 200 W RF 파워를 인가하여 플라즈마를 생성하였고 도핑은 바이어스 전압 -1 kV에서 60 초 동안 실시하였다. 얕은 접합을 형성하기 위한 불순물의 활성화는 ArF(193 nm) excimer laser를 통해 $460\;mJ/cm^2$의 에니지로 열처리를 실시하였다. 그리고 낮은 접촉비저항과 표면저항을 얻기 위해 metal sputter를 통해 TiN/Ti를 $800/400\;{\AA}$ 증착하고 metal RTP를 사용하여 실리사이드 형성 온도를 $650{\sim}800^{\circ}C$까지 60 초 동안 열처리를 실시하여 $TiSi_2$ 박막을 형성하였다. 그리고 $TiSi_2$의 두께를 측정하기 위해 TEM(Transmission Electron Microscopy)을 측정하였다. 화학적 결합상태를 분석하기 위해 XPS(X-ray photoelectronic)와 XRD(X-ray diffraction)를 측정하였다. 접촉비저항, 접촉저항과 표면저항을 분석하기 위해 TLM(Transfer Length Method) 패턴을 제작하여 I-V 특성을 측정하였다. TEM 측정결과 $TiSi_2$의 두께는 약 $580{\AA}$ 정도이고 morphology는 안정적이고 실리사이드 집괴 현상은 발견되지 않았다. XPS와 XRD 분석결과 실리사이드 형성 온도가 $700^{\circ}C$에서 C54 형태의 $TiSi_2$ 박막이 형성되었고 가장 낮은 접촉비저항과 접촉저항 값을 가진다.

• Journal of Radiation Industry
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• v.6 no.1
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• pp.31-40
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• 2012

There are two methods to fabricate the readout electronic to a large-area CMOS image sensor (LACIS). One is to design and manufacture the sensor part and signal processing electronics in a single chip and the other is to integrate both parts with bump bonding or wire bonding after manufacturing both parts separately. The latter method has an advantage of the high yield because the optimized and specialized fabrication process can be chosen in designing and manufacturing each part. In this paper, LACIS chip, that is optimized design for the latter method of fabrication, is presented. The LACIS chip consists of a 3-TR pixel photodiode array, row driver (or called as a gate driver) circuit, and bonding pads to the external readout ICs. Among 4 types of the photodiode structure available in a standard CMOS process, $N_{photo}/P_{epi}$ type photodiode showed the highest quantum efficiency in the simulation study, though it requires one additional mask to control the doping concentration of $N_{photo}$ layer. The optimized channel widths and lengths of 3 pixel transistors are also determined by simulation. The select transistor is not significantly affected by channel length and width. But source follower transistor is strongly influenced by length and width. In row driver, to reduce signal time delay by high capacitance at output node, three stage inverter drivers are used. And channel width of the inverter driver increases gradually in each step. The sensor has very long metal wire that is about 170 mm. The repeater consisted of inverters is applied proper amount of pixel rows. It can help to reduce the long metal-line delay.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.20 no.3
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• pp.29-34
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• 2019

Silicon carbide is considered to be a potentially useful material for high-temperature electronic devices, as its large energy band gap and the p-type and/or n-type conduction can be controlled by impurity doping. Particularly, electric conductivity of porous n-type SiC semiconductors fabricated from ${\beta}-SiC$ powder at $2000^{\circ}C$ in $N_2$ atmosphere was comparable to or even larger than the reported values of SiC single crystals in the temperature region of $800^{\circ}C$ to $1000^{\circ}C$, while thermal conductivity was kept as low as 1/10 to 1/30 of that for a dense SiC ceramics. In this work, for the purpose of decreasing sintering temperature, it was attempted to fabricate porous reaction-sintered bodies at low temperatures ($1400-1600^{\circ}C$) by thermal decomposition of polycarbosilane (PCS) impregnated in n-type ${\beta}-SiC$ powder. The repetition of the impregnation and sintering process ($N_2$ atmosphere, $1600^{\circ}C$, 3h) resulted in only a slight increase in the relative density but in a great improvement in the Seebeck coefficient and electrical conductivity. However the power factor which reflects the thermoelectric conversion efficiency of the present work is 1 to 2 orders of magnitude lower than that of the porous SiC semiconductors fabricated by conventional sintering at high temperature, it can be stated that thermoelectric properties of SiC semiconductors fabricated by the present reaction-sintering process could be further improved by precise control of microstructure and carrier density.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.20 no.6
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• pp.14-18
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• 2019

The conductivity of a semiconductor is primarily determined by the carriers. To achieve higher conductivity, the number of carriers should be high, and an energy trap level is created so that the carriers can cross the forbidden zone with low energy. Carriers have a crystalline binding structure, and interfacial mismatching tends to make them less conductive. In general, high-concentration doping is typically used to increase mobility. However, higher conductivity is also observed in non-orthogonal conjugation structures. In this study, the phenomena of higher conductivity and higher mobility were observed with space charge limiting current due to tunneling phenomena, which are different from trapping phenomena. In an atypical structure, the number of carriers is low, the resistance is high, and the on/off characteristics of capacitances are improved, thus increasing the mobility. ZTO thin film improved the on/off characteristics of capacitances after heat treating at $150^{\circ}C$. In charging and discharging tests, there was a time difference in the charge and discharging shapes, there was no distinction between n and p type, and the bonding structure was amorphous, such as in the depletion layer. The amorphous bonding structure can be seen as a potential barrier, which is also a source of space charge limiting current and causes conduction as a result of tunneling. Thus, increased mobility was observed in the non-structured configuration, and the conductivity increased despite the reduction of carriers.