• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 1996년도 추계학술대회 논문집
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• pp.113-116
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• 1996

The drain current of the MOSFET in the off state(i.e., Id when Vgs=0V) is undesired but nevertheless important leakage current device parameter in many digital CMOS IC applications (including DRAMs, SRAMs, dynamic logic circuits, and portable systems). The standby power consumed by devices in the off state have added to the total power consumed by the IC, increasing heat dissipation problems in the chip. In this paper, hot-carrier-induced degra- dation and gate-induced-drain-leakage curr- ent under worse case in P-MOSFET\`s have been studied. First of all, the degradation of gate-induced- drain-leakage current due to electron/hole trapping and surface electric field in off state MOSFET\`s which has appeared as an additional constraint in scaling down p-MOSFET\`s. The GIDL current in p-MOSFET\`s was decreased by hot-electron stressing, because the trapped charge were decreased surface-electric-field. But the GIDL current in n-MOS77T\`s under worse case was increased.

• 반도체디스플레이기술학회지
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• 제13권3호
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• pp.45-50
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• 2014

In this paper, we propose a super-junction MOSFET (SJ MOSFET) fabricated through a simple pillar forming process by varying the Si epilayer thickness and doping concentration of pillars using SILVACO TCAD simulation. The design of the SJ MOSFET structure is presented, and the doping concentration of pillar, breakdown voltage ($V_{BR}$) and drain current are analyzed. The device performance of conventional Si planar metal-oxide semiconductor field-effect transistor(MOSFET), Si SJ MOSFET, and SiGe SJ MOSFET was investigated. The p- and n-pillars in Si SJ MOSFET suppressed the punch-through effect caused by drain bias. This lead to the higher $V_{BR}$ and reduced on resistance of Si SJ MOSFET. An increase in the thickness of Si epilayer and decrease in the former is most effective than the latter. The implementation of SiGe epilayer to SJ MOSFET resulted in the improvement of $V_{BR}$ as well as drain current in saturation region, when compared to Si SJ MOSFET. Such a superior device performance of SiGe SJ MOSFET could be associated with smaller bandgap of SiGe which facilitated the drift of carriers through lower built-in potential barrier.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 1998년도 추계종합학술대회 논문집
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• pp.597-600
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• 1998

When a semiconductor(pMOSFET) sensor is exposed to ionizing radiation, electrons/holes are generated in its oxide layer. By the phenomenon of hole traps in oxide layer during their move, the characteristics of semiconductor is changed. This paper describes the output characteristic changes of two kind of pMOSFET(domestic, japan) after C0-60 ${\gamma}$-irradiation on them for their application as radiation accumulated dose monitoring sensors. We found the threshold voltage shifts (VT) of pMOSFETs in proportion to irradiated radiation dose and their linear properties. These results make us confirm that we will be able to develop good accumulated radiation dose monitoring sensors.

• E2M - 전기 전자와 첨단 소재
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• 제5권3호
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• pp.320-327
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• 1992

Twin-tub CMOS 공정에 의해 제작된 서브마이크로미터 채널길이를 갖는 n채널 및 p채널 MOSFET의 특성을 고찰하였다. n채널 및 p채널 영역에서의 불순물 프로파일과 채널 이온주입 조건에 따른 문턱전압의 의존성 및 퍼텐셜 분포를 SUPREM-II와 MINIMOS 4.0을 사용하여 시뮬레이션하였다. 문턱전압 조정을 위한 counter-doped 보론 이온주입에 의해 p채널 MOSFET는 표면에서 대략 0.15.mu.m의 깊이에서 매몰채널이 형성되었다. 각 소자의 측정 결과, 3.3[V] 구동을 위한 충분한 여유를 갖는 양호한 드레인 포화 특성과 0.2[V]이하의 문턱전압 shift를 갖는 최소화된 짧은 채널 효과, 10[V]이상의 높은 펀치쓰루 전압과 브레이크다운 전압, 낮은 subthreshold 값을 얻었다.

• 전기전자학회논문지
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• 제17권3호
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• pp.360-364
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• 2013

The maximum breakdown voltage's characteristic within the Super Junction MOSFET structure comes from N-Drift and P-Pillar's charge balance. By developing P-Pillar from Planar MOSFET, it was confirmed that the breakdown voltage is improved through charge balance, and by setting the gate voltage at 10V, the characteristic comparisons of Planar MOSFET and Super Junction MOSFET are shown in picture 6. The results show that it had the same breakdown voltage as Planar MOSFET which increased temperature resistance by 87.4% at $.019{\Omega}cm^2$ which shows that by the temperature resistance increasing, the power module's power dissipation improved.

• 대한전자공학회논문지
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• 제24권3호
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• pp.472-477
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• 1987

In order to prevent the short-channel effects due to threshold voltage adjustment implantation in conventional n+ doped silicon gate process, a new approach involving automatic doping of polycide by boron during source and drain implantation is introduced. P-MOSFET devece fabricated by theis approach shows improved short channel characteristics than conventional device with n+ doped gate. Some concerns of adopting this approach in CMOS technology are addressed togetheer with some suggestions.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2009년도 제40회 하계학술대회
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• pp.1698_1699
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• 2009

핵폭발 등에서 방출되는 과도펄스(Transient pulse) 형태의 방사선이 반도체 소자에 조사되면 소자 내부에서는 짧은 시간에 다량의 전하가 생성된다. 이 전하들이 일정방향으로 증폭된 광전류가 소자의 고장과 오동작을 유발하거나 극단적으로 소진(Burn out)되는 원인이 된다. 본 연구에서는 과도방사선 펄스가 입사하였을 때 pMOSFET 소자 내에 생성되는 전자 정공 쌍(EHP)으로 인해 형성되는 광전류가 소자의 방사선 피해로 나타나는 과정 및 영향을 연구하기 위해 반도체 공정 시뮬레이터를 이용해 전하들의 거동과 광전류 크기를 시뮬레이션하고, 전자가속기에서 실측시험을 병행하였다. 가속기 주변의 전자장을 인한 큰 잡음으로부터 가속기 펄스신호에 의해 pMOSFET에서 발생된 소신호의 광전류를 측정하기 위해서 정밀 신호처리 회로를 구성하였다. 시뮬레이션과 실측시험에서의 결과 비교/분석에서 두 광전류 파형은 유사한 형태를 확인할 수 있었다.

• 전자공학회논문지A
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• 제31A권1호
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• pp.77-83
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• 1994

Characteristics of hot-electron-induced degradation by AC, DC was investigated for p-MOSFET's(W/L=25/l$\mu$m) with sub-10nm RTP-CVD gate oxides. It was confirmed that the surface channel p-MOSFET of a thinner gate oxide shows less degradation. Mechanisms for this effect were analyzed using a simple MOS Device degradation model. It was found that the number of generated electron traps(fixed charge) is determined by the amount of peak gate current, dependent of the gate oxide thickness, and the major cause of the smaller degradation in the thinner gate oxide devices is the lower hot electron trapping carriers.

• 한국전기전자재료학회논문지
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• 제33권2호
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• pp.83-87
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• 2020

In this letter, we propose and analyze a new asymmetric structure that can be used for next-generation power semiconductor devices. We compare and analyze the electrical characteristics of the proposed device with respect to those of symmetric devices. The proposed device has a p-emitter on the right side of the cell. The peak electric field is reduced by the shielding effect caused by the p-emitter structure. Consequently, the breakdown voltage is increased. The proposed asymmetric structure has an approximately 100% higher Baliga's figure of merit (~94.22 MW/㎠) than the symmetric structure (~46.93 MW/㎠), and the breakdown voltage of the device increases by approximately 70%.

• 한국세라믹학회지
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• 제38권10호
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• pp.871-875
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• 2001

Cobalt silicidation at sidewall spacer edge of Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs) with post annealing treatment for capacitor forming process has been investigated as a function of dopant species. Cobalt silicidation of nMOSFET with n-type Lightly Doped Drain (LDD) and pMOSFET with p-type LDD produces a well-developed cobalt silicide with its lateral growth underneath the sidewall spacer. In case of pMOSFET with n-type LDD, however, a void is formed at the sidewall spacer edge with no lateral growth of cobalt silicide. The void formation seems to be due to a retarded silicidation process at the LDD region during the first Rapid Thermal Annealing (RTA) for the reaction of Co with Si, resulting in cobalt mono silicide at the LDD region. The subsequent second RTA converts the cobalt monosilicide into cobalt disilicide with the consumption of Si atoms from the Si substrate, producing the void at the sidewall spacer edge in the Si region. The void formed at the sidewall spacer edge serves as a resistance in the current-voltage characteristics of the pMOSFET device.