• JSTS:Journal of Semiconductor Technology and Science
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• v.3 no.1
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• pp.27-32
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• 2003

Highly reproducible side-wall process for the fabrication of the fine gate length as small as 40nm was developed. This process was utilized to fabricate 40nm InGaAs HEMTs with the 65% strained channel. With the usage of the dual $SiO_2$ and $SiN_x$ dielectric layers and the proper selection of the etching gas, the final gate length (Lg) was insensitive to the process conditions such as the dielectric over-etching time. From the microwave measurement up to 40GHz, extrapolated fT and fmax as high as 371 and 345 GHz were obtained, respectively. We believe that the developed side-wall process would be directly applicable to finer gate fabrication, if the initial line length is lessened below the l00nm range.

• Journal of the Korean Vacuum Society
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• v.22 no.6
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• pp.335-340
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• 2013

This paper is for the simulation design to enhance the breakdown voltage of MHEMTs with an InP-etchstop layer. Gate-recess and channel structures has been simulated and analyzed for the breakdown of the MHEMT devices. The fully removed recess structure at the drain side of MHEMT shows that the breakdown voltage enhances from 2 V to almost 4 V as the saturation current at gate voltage of 0 V is reduced from 90 mA to 60 mA at drain voltage of 2 V. This is because the electron-captured negatively fixed charges at the drain-side interface between the InAlAs barrier and the $Si_3N_4$ passivation layers deplete the InGaAs channel layer more and thus decreases the electron current passing the channel layer and thus the impact ionization in the channel become smaller. In addition, the replaced InGaAs/InP composite channel with the same thickness in the same asymmetrically recessed structure increases the breakdown voltage to 5 V due to the smaller impact ionization and mobility of the InP layer at high drain voltage.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2001.07a
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• pp.828-831
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• 2001

A simple and versatile method of manufacturing semiconductor devices with pn-junctions used the silicon direct bonding technology with simultaneous impurity diffusion is suggested . Formation of p- or n- type layers was tried during the bonding procedure by attaching two wafers in the aqueous solutions of Al(NO$_3$)$_3$, Ga(NO$_3$)$_3$, HBO$_3$, or H$_3$PO$_4$. An essential improvement of bonding interface structural quality was detected and a model for the explanation is suggested. Diode, Dynistor, and BGGTO structures were fabricated and examined. Their switching characteristics are presented.