• Journal of the Korea Institute of Information and Communication Engineering
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• v.10 no.2
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• pp.303-307
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• 2006

In this paper, we have designed the p-type metal-oxide semiconductor field-effect transistor(pMOSFET) for SiGe devices with gate lengths of $0.9{\mu}m$ and $0.1{\mu}m$using the TCAD simulators. The electrical characteristics of devices have been investigated over the temperatures of 300 and 77K. We have used the two carrier transfer models(hydrodynamic model and drift-diffusion model). We how that the drain current is higher in the hydrodynamic model than the drift-diffusion model. When the gate length is $0.9{\mu}m$, the threshold voltage shows -0.97V and -1.15V for 300K and 77K, respectively. The threshold voltage is, however, nearly same at $0.1{\mu}m$ for 300K and 77K.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.31 no.6
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• pp.372-376
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• 2018

The effects of off-state bias stress on the characteristics of p-type poly-Si TFT were investigated. To reduce the gate-induced drain leakage (GIDL) current, the off-state bias stress was changed by varying Vgs and Vds. After application of the off-state bias stress, the Vgs causing GIDL current was dramatically increased from 1 to 10 V, and thus, the Vgs margin to turn off the TFT was improved. The on-current and subthreshold swing in the aged TFT was maintained. We performed a technology computer-aided design (TCAD) simulation to describe the aged characteristics. The aged-transfer characteristics were well described by the local charge trapping. The activation energy of the GIDL current was measured for the pristine and aged characteristics. The reduced GIDL current was mainly a thermionic field-emission current.

• Journal of Sensor Science and Technology
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• v.8 no.5
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• pp.421-426
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• 1999

In this paper, we present p-channel GaAs MOSFET having $Al_2O_3$ as gate insulator fabricated on a semi-insulating GaAs substrate, which can be operated in the depletion mode. $1\;{\mu}m$ thick undoped GaAs buffer layer, $4000\;{\AA}$ thick p-type GaAs epi-layer, undoped $500{\AA}$ thick AlAs layer, and $50\;{\AA}$ thick GaAs cap layer were subsequently grown by molecular beam epitaxy(MBE) on (100) oriented semi-insulating GaAs substrate and this wafer was oxidized. AlAs layer was fully oxidized as a $Al_2O_3$ thin film. The I-V, $g_m$, breakdown charateristics of the fabricated GaAs MOSFET showed that wet thermal oxidation of AlAs/GaAs epilayer/S I GaAs was successful in realizing depletion mode p-channel GaAs MOSFET.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2010.05a
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• pp.226-229
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• 2010

LED(Light Emitting Diode) is an emitting device which energy is same to the bandgap of p-type and n-type semiconductor junction. Recently high brightness LED is used in fish-luring light and traffic signal light alternative of normal light bulb, and widely used in the area of display pannel. Moreover nowadays LED has been used as a back light of LCD display. Recently, visible light communication(VLC) using LED, that allow two-way serial data communication between LEDs over a distance of sveral centimeters or meters, has been widely studied in the area of digital information transmission along with illumination and display. In this paper, we present LED communication system and their applications.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2007.06a
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• pp.11-11
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• 2007

1차원 구조체인 반도체 나노선은 앙자제한효과 (quantum confinement effect) 등을 이용하여 고밀도/고효율의 소자 개발이 기대되고 있다. GaN는 상온에서 3.4 eV의 밴드갭 에너지를 갖는 III-V 족 반도체 재료로써 박막의 경우 광전자 소자로 폭넓게 응용되고 있다. 최근 GaN 나노선의 합성에 성공하면서 발광소자, 고효율의 태양전지, HEMT 등으로의 응용을 위한 많은 연구가 활발히 이루어지고 있다. 하지만, 아직까지 GaN 나노선의 전기적 특성을 제어하는 기술은 확립되지 않고 있다. 본 연구에서는 Vapor solid (VS)법을 이용하여 GaN 나노선을 합성하였으며, GaN 분말과 함께 $Mg_2N_3$ 분말을 첨가하여 (Ga,Mg)N 나노선을 성공적으로 합성하였다. 합성시에 GaN와 Mg 소스간의 거리 변화를 통해 Mg 도핑농도를 제어하고자 하였다. 이 같은 방법으로 합 된 (Ga,Mg)N 나노선의 Mg 도핑농도에 따른 결정학적 특성을 알아보고, (Ga,Mg)N 나노선을 이용하여 소자를 제작한 후 그 전기적 특성을 살펴보고자 한다. X-ray diffraction (XRD)과 high-resolution transmission electron microscopy (HRTEM), EDX를 이용하여 합성된 나노선의 결정학적 특성과 Mg의 도핑 농도를 확인하였다. Photo lithography와 e-beam lithography법을 이용하여 (Ga,Mg)N 나노선 field-effect transistor (FET)를 제작하고, channel current-drain voltage ($I_{ds}-V_{ds}$) 와 channel current-gate voltage ($I_{ds}-V_g$) 측정을 통해 (Ga,Mg)N 나노선이 도핑 농도에 따라 n형에서 p형으로 전기적 특성이 변화함을 확인하였다.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2007.06a
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• pp.48-48
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• 2007

P-type transparent conducting $CuGaO_2$ thin films have been prepared by DC/RF sputtering using Quartz(0001) and sapphire(0001) substrates. The target was fabricated by heating a stoichiometric mixture of CuO and $Ga_2O_3$ at 1373K for 12h under $N_2$ atmosphere. The film were deposited under mixture gas of Ar and $O_2(Ar:O_2=4:1)$ during 10~30min. and the as-deposited films were annealed at 1123K and $N_2$ atmosphere. Room temperature conductivity and the activation energy of the sintered body in the temperature range of 223K ~ 423K were 0 004S/cm, 1.9eV, respectively. XRD revealed that all of the as-deposited films were amorphous. Heating of the films deposited on Quartz substrates above 1123K resulted in crystallization with a second phase of $CuSiO_3$, which was assumed owing to reaction with Quartz substrate. The single phase of $CuGaO_2$ was obtained at the film deposited on the sapphire substrates. The transmittance after annealing of DC- and RF-sputtered films were 55~75% at 550nm. From the transmittance and reflectance measurement. the direct band gap of the DC/RF-sputtered films were 3.63eV and 3.57eV. and there was little difference between DC and RF sputtered films.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2005.07a
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• pp.141-142
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• 2005

To investigate the ZnO thin films which is interested in the next generation of short wavelength LEDs and Lasers, our ZnO thin films were deposited by RF sputtering system. At sputtering process of ZnO thin films, substrate temperature, work pressure respectively is $300^{\circ}C$ and 5.2 mTorr, and the purity of target is ZnO 5N. The thickness of ZnO thin films was about $1.9{\mu}m$ at SEM analysis after sputtering process. Phosphorus (P) and arsenic (As) were diffused into ZnO thin films sputtered by RF magnetron sputtering system in ampoule tube which was below $5\times10^{-7}$ Torr. The dopant sources of phosphorus and arsenic were $Zn_3P_2$ and $ZnAs_2$. Those diffusion was perform at 500, 600, and $700^{\circ}C$ during 3hr. We find the condition of p-type ZnO whose diffusion condition is $700^{\circ}C$, 3hr. Our p-type ZnO thin film has not only very high carrier concentration of above $10^{19}/cm^3$ but also low resistivity of $5\times10^{-3}{\Omega}cm$.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.24 no.6
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• pp.433-439
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• 2011

Poly Si TFTs (poly silicon thin film transistors) with p channel those are annealed HT (high temperature) with gate poly crystalline silicon and LT (low temperature) with metal gate electrode were fabricated on quartz substrate using the analyzed data and compared according to the activated grade silicon thin films and the size of device channel. The electrical characteristics of HT poly-Si TFTs increased those are the on current, electron mobility and decrease threshold voltage by the quality of particles of active thin films annealed at high temperature. But the on/off current ratio reduced by increase of the off current depend on the hot carrier applied to high gate voltage. Even though the size of the particles annealed at low temperature are bigger than HT poly-Si TFTs due to defect in the activated grade poly crystal silicon and the grain boundary, the characteristics of LT poly-Si TFTs were investigated deterioration phenomena those are decrease the electric off current, electron mobility and increase threshold voltage. The results of transconductance show that slope depend on the quality of particles and the amplitude depend on the size of the active silicon particles.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.23 no.7
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• pp.513-516
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• 2010

In this work, a study is presented of the static characteristics of 4H-SiC DMOSFETs obtained by adjustment of the p-base region. The structure of this MOSFET was designed by the use of a device simulator (ATLAS, Silvaco.). The static characteristics of SiC DMOSFETs such as the blocking voltages, threshold voltages, on-resistances, and figures of merit were obtained as a function of variations in p-base doping concentration from $1\;{\times}\;10^{17}\;cm^{-3}$ to $5\;{\times}\;10^{17}\;cm^{-3}$ and doping depth from $0.5\;{\mu}m$ to $1.0\;{\mu}m$. It was found that the doping concentration and the depth of P-base region have a close relation with the blocking and threshold voltages. For that reason, silicon carbide DMOSFET structures with highly intensified blocking voltages with good figures of merit can be achieved by adjustment of the p-base depth and doping concentration.

• Proceedings of the Korean Vacuum Society Conference
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• 2000.02a
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• pp.71-71
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• 2000

본 연구에서는 차세대 마이크로파 유전체 소자로서의 응용을 목적으로 펄스 레이저 방식에 의하여 증착된 MgTiO3 박막의 전기적 특성을 종합적으로 연구 분석하였다. 이를 바탕으로 MgTiO3 박막의 유전손실 등과 같은 열화를 야기시키는 박막 내부 또는 박막과 기판간의 결함의 특성을 파악하여 열화 메카니즘을 분석하였다. MgTiO3는 마이크로파 영역에서의 우수한 유전특성과 같은 낮은 유전손실을 가지며, 온도 안정성 또한 우수하다. 현재까지 벌크 세라믹 MgTiO3 의 응용 광범위하게 연구되어 왔으나 박막의 제조공정 및 전기적 특성 분석은 미흡한 형편이다. 따라서 벌크 세라믹과는 특성이 상이한 박막의 전기적 특성분석 및 연구가 필요하다. 분석을 위한 소자의 기본 구조로서 Metal-Insulator-Semiconductor(MIS) 구조를 채택하였다. MgTiO3 박막을 증착하기 위한 기판으로는 n형 Si(100)기판과 p형 Si(100)기판을 사용하였고, Si 기판 위에 급속 열처리기 (RTP)를 이용하여 SiO2를 ~100 두께로 성장시킨 것과 성장시키지 않은 것으로 구분하여 제작하였다. MgTiO3 박막은 펄스 레이저 증착 방식(PLD)에 의하여 약 2500 두께로 증착되었으며, 200mTorr 압력의 산소 분위기 하에서 기판의 온도를 40$0^{\circ}C$~55$0^{\circ}C$까지 5$0^{\circ}C$간격으로 변화시키며 제작하였다. 상하부의 전극 금속으로는 Al을 이용하였으며, 열증발 증착기로 증착하였다. 증착된 MgTiO3 박막의 결정구조를 확인하기 위하여 XRD 분석을 수행하였으며, 박막의 전기적 특성을 분석하기 위해 Boonton7200 C-V 측정기와 HP4140P를 이용한 경우에는 C-V 곡선에 이력현상이 나타났으나, MgTiO3/SiO2를 이용한 경우에는 이력현상이 나타나지 않았고, 유전율은 감소하는 것으로 나타났다. I-V 측정 결과, 절연층으로 MgTiO3/SiO2를 이용한 경우에는 MgTiO3만을 절연층으로 사용한 경우에 비해 동일한 전계에서 낮은 누설전류 값을 가짐을 알 수 있었다. 또한 박막의 증착온도가 증가함에 따라서 C-V 곡선의 위치가 양의 방향으로 이동함을 확인하였다. 위의 현상은 기판의 종류에 관계없이 발생하는 것으로 보아 벌크 또는 계면에 존재하는 결함에 의한 것으로 추정된다. 현재 C-V 곡선의 이동 원인과 I-V 곡선의 누설전류 메카니즘을 분석 중에 있으며 그 결과를 학회에서 발표할 예정이다.