• 대한전기학회:학술대회논문집
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• 대한전기학회 2004년도 학술대회 논문집 정보 및 제어부문
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• pp.231-233
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• 2004

Queuing is waiting lines which play routing service when packet entered. Queuing is decide how and whom is going to provide priority service. This is kind of first in first out(FIFO) or weighted fair queuing(WFQ) method. In this study, UDP design using WFQ way to serve to provide service evenly and rapidly in network. Also in actuality internet, datagram analyzed by packet captured. Queuing services through the requesting port number, input, output, output queuing creation & delete, message request by internet control message protocol(ICMP). Queuing designed in control block module, input queues, input/output module composition. In conclusion, I have confirm queuing result of WFQ method by the datagram information analyzed.

• 한국정보처리학회논문지
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• 제6권2호
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• pp.459-466
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• 1999

I broadband ISDN every packet will show different result if it would be processed according to its usage by the server. That is, normal data won't show big differences if they would be processed at normal speed. But it will improve the quality of service to process some kinds of data - for example real time video or voice type data or some data for a bid to by something through the internet - more fast than the normal type data. solution for this problem was suggested - priority packets. But the analyses of them are under way. Son in this paper a switching system for an output queuing model in a single server was assumed and some packets were given priorities and analysed. And correlation, simulating real life situation, was given too. These packets were analysed through three cases, first packets having no correlation, second packets having only correlation and finally packets having priority three cases, first packets having no correlation, second packets having only correlation and finally packets having priority and correlation. The result showed that correlation doesn't affect the mean delay time and the high priority packets have improved mean delay time regardless of the arrival rate. Those packets were assumed to be fixed-sized like ATM fixed-sized cell and the contention strategy was assumed to be short bus contention method for the output queue, and the mean delay length and the maximum 버퍼 length not to lose any packets were analysed.

• Journal of Communications and Networks
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• 제1권3호
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• pp.145-152
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• 1999

A new switch architecture is presented to enhance out-put queuing in photonic packet switches. Its appkication is for a packet switching enviroment based on the optical transport of fixed length packets. This architecture consists of a couple of cas-cading switching elements with output queuing, whose buffer ca-pacity is limited by photonic technology. The introduction of a suitable buffer management allows a very good and balanced ex-ploitation of the available optical memories, realized with fiber de-lay lines. In particular, packet loss performance is here evaluated showing the improvement with respect to the single switch and a way to design large optical switches is shown in order to meet broadband network requirements.

• ETRI Journal
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• 제28권1호
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• pp.31-44
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• 2006

In a packet switching network, congestion is unavoidable and affects the quality of real-time traffic with such problems as delay and packet loss. Packet fair queuing (PFQ) algorithms are well-known solutions for quality-of-service (QoS) guarantee by packet scheduling. Our approach is different from previous algorithms in that it uses hardware time achieved by sampling a counter triggered by a periodic clock signal. This clock signal can be provided to all the modules of a routing system to get synchronization. In this architecture, a variant of the PFQ algorithm, called digitized delay queuing (DDQ), can be distributed on many line interface modules. We derive the delay bounds in a single processor system and in a distributed architecture. The definition of traffic contribution improves the simplicity of the mathematical models. The effect of different time between modules in a distributed architecture is the key idea for understanding the delay behavior of a routing system. The number of bins required for the DDQ algorithm is also derived to make the system configuration clear. The analytical models developed in this paper form the basis of improvement and application to a combined input and output queuing (CIOQ) router architecture for a higher speed QoS network.

• 한국정보과학회:학술대회논문집
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• 한국정보과학회 2004년도 가을 학술발표논문집 Vol.31 No.2 (3)
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• pp.301-303
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• 2004

현재 ATM 망에서 다양한 형태의 스위치 구조가 제안 되었으며 스위치 구조는 크게blocking 과 nonblocking 스위치로 나눌 수 있다. nonblocking 스위치는 버퍼의 위치에 따라 input queuing, output queuing, shared buffer switch로 나뉘며 그 중에 입력 버퍼형은 하드웨어 구현이 쉬운 장점이 있으나 HOL블로킹으로 인하여 처리 효율이 낮다는 단점이 있다. 본 논문에서는 이러한 입력 버퍼형 ATM 교환기의 문제점을 해결하기 위하여 가상적인 입력버퍼와 MUX를 이용한 입력버퍼형 반얀 스위치 모델을 제안한다.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 1998년도 추계종합학술대회 논문집
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• pp.75-78
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• 1998

In this paper, we propose a new cell discarding and scheduling scheme which reduce cell loss rate by measuring, in real time, the number of discarded cells in the queuing system with a different loss priority for each class of service such that each class of service meets its cell loss rate requirements and reduce average delay rate for the traffic that is sensitive in cell delay in output buffer of the ATM switch. Throughout the computer simulation, the existing scheduling scheme and proposed scheme are compared with respect to cell loss rate and average delay time.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 1998년도 하계종합학술대회논문집
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• pp.769-772
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• 1998

This paper present an efficient techniques for visual inspection of taped electronic parts, suitable for real time implementation. The main environments of developed system are IBM-compatible personal computer, frame grabber, digital input-output board. It is connected to the programmable logic controller unit of the taping machine in real time. Using a queuing structure, operator or extractor machine can remove easily the defect one from production line. Also, we design a new illumination system for sacquring shape and subface features of object. Therefore, it redue pre-processing step and processing time.

• 한국시뮬레이션학회논문지
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• 제1권1호
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• pp.31-36
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• 1992

To estimate the probability of long delay in a queuing system using discrete-event simulation is studied. We contrast the coverage, half-width, and stability of confidence intervals constructed using two methods: batch means and new resampling technique; binary bootstrap. The binary bootstrap is an extension of the conventional bootstrap that resamples runs rather than data values. Empirical comparisons using known results for the M/M/1 and D/M/10 queues show the binary bootstrap superior to batch means for this problem.

• 한국시뮬레이션학회:학술대회논문집
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• 한국시뮬레이션학회 1992년도 제2회 정기총회 및 추계학술 발표회 발표논문 초록
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• pp.13-13
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• 1992

To estimate the probability of long delay in a queuing system using discrete-event simulation studied. We contrast the coverage, half-width, and stability of confidence intervals constructed using two methods: batch means and new resampling technique; binary bootstrap. The binary bootstrap is an extension of the conventional bootstrap that resamples runs rather than data values. Empirical comparisons using known results for the M/M/1 and D/M/10 queues show the binary bootstrap superior to batch means for this problem.

• 한국정보과학회논문지:컴퓨팅의 실제 및 레터
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• 제14권3호
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• pp.311-315
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• 2008

최근 인터넷 망에서 고속 스위칭을 위하여 입출력 인터페이스 간 패킷 전송에 있어서 스위칭 패브릭이 적용되고 있다. 기존의 구조들은 가변 길이 IP 패킷의 처리에 ATM 스위칭 패브릭을 그대로 적용하기 위해 패킷을 일정 크기로 분할 및 재조립하거나 크로스포인트에 버퍼를 두는 방식을 고려하고 있어 시스템에 부하를 가져온다. 본 논문에서는 데이타 메모리 평면과 스위칭 평면을 분리하여 패킷 데이타는 독립된 메모리 구조에 저장하고 동시에 메모리 주소 포인터 부분만 스위칭 패브릭을 통과하도록 하는 새로운 스위치 구조를 제안한다. 스위칭 패브릭은 주소 포인터와 기본적인 정보를 포함하는 아주 작은 미니 패킷이 통과하게 되는데 이것은 가변길이 패킷들이 경쟁하는 스위칭 패브릭과 비교할 때 탁월한 스위칭 속도를 가진다.