• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2014.11a
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• pp.10-11
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• 2014

In a 2-dimensional (2D) Discrete Cosine Transform (DCT) hardware, a significant fraction of the total hardware area is contributed by the combinational logic used to perform 1-dimensional (2D) transform. The size of the non-combinational logic i.e. the transpose memory is dictated by the size of the largest transform supported. Hence, the optimization of hardware area is performed mainly for 1D-transform combinational logic. This paper demonstrates the use of Multiple Constant Multiplication (MCM) algorithm to reduce the combinational logic area. Partial optimizations are also described for the cases where the direct use of MCM algorithm doesn't meet the timing constraint. Experimental results show that 46% improvement in gate count is achieved for 32 point 1D DCT transform logic after using MCM optimization.

• Journal of Computing Science and Engineering
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• v.6 no.4
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• pp.294-309
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• 2012

In the age of multi-core and specialized accelerators in high performance computing (HPC) systems, it is critical to understand application characteristics and apply suitable optimizations in order to fully utilize advanced computing system. Often time, the process involves multiple stages of application performance diagnosis and a trial-and-error type of approach for optimization. In this study, a general guideline of performance optimization has been demonstrated with two class-representing applications. The main focuses are on node-level optimization and inter-node scalability improvement. While the number of optimization case studies is somewhat limited in this paper, the result provides insights into the systematic approach in HPC applications performance engineering.

• Architectural research
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• v.11 no.2
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• pp.19-26
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• 2009

The effect of rebirthing technique on the genetic algorithm (GA)-based size optimization is investigated. The GA mimics the principles of nature and it can gradually improve structural design through biological operations such as fitness, selection, crossover and mutation. However, premature optimum has been often detected in the generic GA with continuous design variable. Since then, the so-called rebirthing technique has been proposed to avoid this problem. However, the performance of the rebirthing technique has not been reported. Therefore, the size optimizations of spatial structures are tackled to investigate the performance of the rebirthing technique on the generic GA. From numerical results, it is well proved that the rebirthing technique is very effective to produce the optimum values regardless of the values of parameters used in the GA operations.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1997.04a
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• pp.168-171
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• 1997

TFT2DS was developed to provide the usefulness as an analytic and design tool. The static characteristics of a-Si:H TFTs demonstrated a good agreement between simulated and measured data. This paper shows that TFT2DS can optimize the physical parameters of a-Si:H through sensitivity simulations and compute the static characteristics of a-Si:H TFTs. Moreover, through the sensitivity study of the parameters, it is shown that the optimizations of both the physical parameters of a-Si:H and the parameters of a-Si:H deposition, which must be inter-related, might be possibl.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.44 no.8
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• pp.62-67
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• 2007

In some wireless sensor networks, the sensor nodes are required to be located sparsely at designated positions over a wide area, introducing the problem of adding minimum number of relay nodes to interconnect the sensor nodes. The problem finds its form in literature: the Minimum number of Steiner Points. Since it is known to be NP-hard, this paper proposes an approximation scheme to estimate the minimum number of relay nodes through the properties of the abstract from. Reducing the number of nodes in a sensor network, the amount of data exchange over the net will be far decreased.

• JSTS:Journal of Semiconductor Technology and Science
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• v.12 no.1
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• pp.24-33
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• 2012

This paper describes a multi-mode LDPC decoder which supports 19 block lengths and 6 code rates of Quasi-Cyclic LDPC code for Mobile WiMAX system. To achieve an efficient implementation of 114 operation modes, some design optimizations are considered including block-serial layered decoding scheme, a memory reduction technique based on the min-sum decoding algorithm and a novel method for generating the cyclic shift values of parity check matrix. From fixed-point simulations, decoding performance and optimal hardware parameters are analyzed. The designed LDPC decoder is verified by FPGA implementation, and synthesized with a $0.18-{\mu}m$ CMOS cell library. It has 380,000 gates and 52,992 bits RAM, and the estimated throughput is about 164 ~ 222 Mbps at 56 MHz@1.8 V.

• JSTS:Journal of Semiconductor Technology and Science
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• v.17 no.1
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• pp.79-85
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• 2017

In this paper, several optimizations are proposed to enhance the quality of lane detection algorithms in automotive applications. Considering the diagonal directions of lanes, the proposed limited Hough transform newly introduces image-splitting and angle-limiting schemes that relax the number of possible angles at the line voting process. In addition, unnecessary edges along the horizontal and vertical directions are pre-defined and removed during the edge detection procedures, increasing the detecting accuracy remarkably. Simulation results shows that the proposed lane recognition algorithm achieves an accuracy of more than 90% and a computing speed of 92 frame/sec, which are superior to the results from the previous algorithms.

• Proceedings of the Korea Concrete Institute Conference
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• 2000.10a
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• pp.253-258
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• 2000

Recently, the area of design optimization, especially structural optimization, has been and to be a continuous active area of research. And the design optimizations of port facilities have been achieved by many other civil engineers. But the design optimization of port facilities were limited to the design optimization of the breasting dolphin. This paper invested the design optimization of mooring pier and the foundations of mooring pier was suggested considering the convenience of repair and reinforcement work. The mooring pier devised with prestressed precast concrete panel and rigid frame welded wide flange beam to steel pipe pile. To accomplish the design optimization of mooring pier, the Augmented Lagrangian Multiplier Method(ALM) of ADS(Garret N. Vanderplaats) optimization routine, BFGS method as optimizer and Golden Section Method as one dimensional search were utilized. As a result, thirty percent of material cost for construction was reduced by design optimization. The tensile stress of concrete panel and bottom flage was critical constraints under service load. So, using high strength concrete and steel will be economical. And lots of initial values must be invested to accomplish the design optimization in design procedures.

• Speech Sciences
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• v.14 no.4
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• pp.157-167
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• 2007

In this paper, we implemented a single-chip speech recognizer using the TMS320C2000 DSPs. For this implementation, we had developed very small-sized speaker-dependent recognition engine based on dynamic time warping, which is especially suited for embedded systems where the system resources are severely limited. We carried out some optimizations including speed optimization by programming time-critical functions in assembly language, and code size optimization and effective memory allocation. For the TMS320F2801 DSP which has 12Kbyte SRAM and 32Kbyte flash ROM, the recognizer developed can recognize 10 commands. For the TMS320F2808 DSP which has 36Kbyte SRAM and 128Kbyte flash ROM, it has additional capability of outputting the speech sound corresponding to the recognition result. The speech sounds for response, which are captured when the user trains commands, are encoded using ADPCM and saved on flash ROM. The single-chip recognizer needs few parts except for a DSP itself and an OP amp for amplifying microphone output and anti-aliasing. Therefore, this recognizer may play a similar role to dedicated speech recognition chips.

• Journal of information and communication convergence engineering
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• v.16 no.3
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• pp.197-202
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• 2018

This paper reveals the impact of the insertion of electromagnetic band gap (EBG) structures on the performance of circularly polarized (CP) patch-slot antenna with offset slot. Several optimizations are necessary to precise physical parameters in the aim to fix the resonance frequency at 3.2 GHz. The proposed antenna possesses lightweight, simplicity, low cost, and circular polarization ensured by two feeding sources to permit right-hand and left-hand circular polarization process (RHCP and LHCP). The measured results compared with simulation results of the proposed circularly polarized EBG antenna with offset slot show good band operations with –10 dB impedance bandwidths of 9.1% and 36.2% centered at 3.2 GHz, which cover weather radar, surface ship radar, and some communications satellites bands. Our investigation will confirm the simulation and experimental results of the EBG antenna involving new EBG structures.