• 한국전기전자재료학회논문지
• /
• 제32권4호
• /
• pp.313-319
• /
• 2019

Induction motors connected with a three-phase AC system may malfunction due to reverse phase or open phase faults. Conventional overcurrent relays and overheating relays are used to prevent such accidents; however, their drawbacks include a low response speed and false operation. Therefore, in this study, a digital relay for the reverse-open phase was designed and fabricated. This relay can detect the reverse phase and open phase faults and send a trigger signal to the control circuit. The proposed relay was developed based on a microcontroller. The detection times of the reverse phase and open phase were verified as 320ms and 80ms, respectively. Compared with conventional relays that only protect the motor from one type of fault, the proposed relay can detect both, reverse phase and open phase faults. In addition, the fault detection, identification criterion, and trigger signal patterns can be modified by programming according to the requirements of users.

• 대한전기학회:학술대회논문집
• /
• 대한전기학회 1987년도 전기.전자공학 학술대회 논문집(II)
• /
• pp.1185-1187
• /
• 1987

Digital systems are increasingly being used in the ranges of many control engineering. The residue number system offers the possibility of high speed operation and error correction. The compact self-checking pulse-train residue arithmetic circuit is proposed. A fault tolerant digital filter is practically implemented using these proposed circuits.

• 한국정보처리학회논문지
• /
• 제4권2호
• /
• pp.628-638
• /
• 1997

VSLI회로에서 스위치 레벨 결함 모델은 stuck-at결함만 사용하는데 한계가 있다. 따라서 본 연구는 스위치 레벨 결함 모델인 트랜지스터 stuck-open과 stuck-close결함을 다룰 수 있는결함 시뮬레이터를 구현한다. 스위치 레벨 회로는 이론적으로 신호 흐름이 양방향으로 전달되지만 실제로 대부분의 신호 흐름은 약 95%정도가 단 방향을로 설정되어 평가되는 것으로 나타내고 있다. 본 연구에서는 스위치 레벨 회로를 단반향 그래프 모델 로 변환시켜 해석한다. 스위치 레벨 회로는 EDIF컴파일러에 의해 입력되고 두개의 단방향으로 재구성된 자료구조를 만든다. 스위치 레벨 회로는 신호 흐름 경로가 도입되는 지배적 경로 기법이 제시된다. 지배적 경로는 경로를 판단하여 최종 출력 상태값을 결정하는 논리 시뮬레이션을 수행한다. 스위치 레벨 결함 시뮬레이션은 노들들로 연결되는 경로 상에 임의 트랜지스터의 stuck-open,stuck-close 결함을 주입시키고, 트랜지스터 저항값을 적용한 노드세기의 계산에 의한 지배적 경로를 평가한다. 이때 최초 입력은 two pattern vector를 인가하여 정상회로의 최종 출력 상태값과 결함회로의 출력 상태값을 비교하여 결함 검색하며, 그결함 검색의 정확성 을 보인다.

• 대한전자공학회논문지
• /
• 제27권11호
• /
• pp.42-48
• /
• 1990

본 논문에서는 CMOS 회로의 stuck-open 고장 검출을 위한 로브스트(robust)테스트 생성방법을 제안한다. CMOS 회로에 대한 입력 벡터들간의 비트(bit)위치와 해밍중(Hamming weight)의 관계를 고려하여 초기화 패턴을 구함으로써 stuck-open 고장검출을 위한 테스트 생성 시간을 감소시킬 수 있으며, 고장검출을 어렵게하게 하는 입력변이지연(input transition skew)의 문제를 해결하고, 테스트 사이퀸스의 수를 최소화시킨다. 또한 회로에 인가할 초기화 패턴과 테스트 패턴간의 해밍거리(hamming distance)를 고려하여 테스트 사이퀸스를 배열하므로써 테스트 사이퀸스의 수를 감소시킨다.

• 전기학회논문지
• /
• 제58권8호
• /
• pp.1538-1543
• /
• 2009

The electric ballast for ceramic metal halide lamp needs a protection circuit to prevent from over voltage and over current in the case that the lamp or the electric ballast are in faults. In this paper, cost-effective and high performance protection circuit is proposed for the electric ballast. The proposed protection circuit is adapted to the electric ballast with $LC_SC_P$ resonance type half bridge inverter. The experimental results demonstrate that the proposed circuit can protect effectively under open and short fault conditions.

• 대한전기학회:학술대회논문집
• /
• 대한전기학회 2000년도 하계학술대회 논문집 A
• /
• pp.185-187
• /
• 2000

Fault current is flowed into 154/23kV M. Tr when line-to-ground fault occurs in power system. NGR(Neutral Grounded Reactor) is set up in order to prevent M.Tr fault by limiting magnitude of fault currents. Here, disconnection of NGR causes voltage increase by L-C resonance and line-to-ground fault in an unearthed system results in voltage increase at healthy phases. So Over Voltage Ground Relay(OVGR) is used for tripping M.Tr. Also, buses at second phases of M.Trs are all connected with section circuit breakers closed for the purpose of parallel operation and load shedding. In case of speciality buses are comprised of power cable in part for GIS connection. When no-load charged cable or bus is open by a section CB, unbalanced voltage charged on the bus is induced. Also discrepant opening time for circuit breakers on different phases gives rise to unbalanced zero sequence voltage. It was observed that this zero sequence voltage detected in the 22.9kV P.T (Potential Transformer for bus) mal-operated 59GT and tripped M.Tr. The zero sequence voltage of which vanishing time is longer than relay operating time came out by EMTDC simulation. Also, it was shown that the voltage waves of actual test are similar to those of simulation. On the basis of above results, R-C circuit complement on the relay without any effect on a power system made operating time of the relay longer than vanishing time of distorted waves. Consequently, operating time of the relay was delayed and magnitude of distorted waves was decreased by increasing time constant of the relay.

• 조명전기설비학회논문지
• /
• 제24권1호
• /
• pp.112-116
• /
• 2010

본 논문에서는 고장발생 초기에 초전도 전류제한기를 구성하는 초전도 소자의 ��치발생을 검출하여 고장전류의 경로를 별도의 상전도 전류제한기로 우회시킴으로써 초전도 전류제한기의 회복시간을 단축시킬 수 있는 초전도소자의 트리거를 이용한 초전도 전류제한기의 전류제한 및 회복특성에 대해 분석하였다. 고장전류 크기를 조절하기 용이한 구성요소로 상전도 전류제한기의 저항크기에 따른 초전도 전류제한기를 구성하고 있는 전력용스위치의 개방시점과 투입시점의 변화를 비교하였으며, 분석을 통해 상전도 전류 제한기의 저항이 증가할수록 초전도 전류제한기를 구성하는 전력용스위치의 복귀시간이 길게 나타남을 확인할 수 있었다.

• 전기학회논문지
• /
• 제65권9호
• /
• pp.1583-1589
• /
• 2016

This paper proposes an improved spread spectrum time domain reflectometry (ISSTDR) using time-frequency correlation and reference signal elimination method in order to have more accurate fault determination and location detection than conventional (SSTDR) despite increased signal attenuation due to the long distance to cable fault location. The proposed method has a two-step process: the first step is to detect a peak location of the reference signal using time-frequency correlation analysis, and the second step is to detect a peak location of the correlation coefficient of the reflected signal by removing the reference signal. The proposed method was validated through comparison with existing SSTDR methods in open-and short-circuit fault detection experiments of low voltage power cables. The experimental results showed that the proposed method can detect correlation coefficients at fault locations accurately despite reflected signal attenuation so that cable faults can be detected more accurately and clearly in comparison to existing methods.

• 전자공학회논문지A
• /
• 제31A권10호
• /
• pp.173-184
• /
• 1994

BiCMOS circuits mixed with CMOS and bipolar technologies show peculiar fault characteristics that are different from those of other technoloties. It has been reported that because most of short faults in BiCMOS circuits cause logically intermediate level at outputs, current monitoring method is required to detect these faluts. However current monitoring requires additional hardware capabilities in the testing equipment and evaluation of test responses can be more difficult. In this paper, we analyze the characteristics of faults in BiCMOS circuit together with their test methods and propose a new design technique for testability to detect the faults by logic monitoring. An effective method to detect the transition delay faults induced by performance degradation by the open or short fault of bipolar transistors in BiCMOS circuits is presented. The proposed design-for-testability methods for BiCMOS circuits are confirmed by the SPICE simulation.

• 전력전자학회논문지
• /
• 제27권1호
• /
• pp.33-39
• /
• 2022

A multi-phase brushless direct current (BLDC) motor is widely used in large-capacity electric propulsion systems such as submarines and electric ships. In particular, in the field of military submarines, the polyphaser motor must suppress torque ripple in various failure situations to reduce noise and ensure stable operation for a long time. In this paper, we propose a polyphaser current control method that can improve efficiency and reduce torque ripple by minimizing the increase in stator winding loss at maximum output torque by controlling the phase angle and amplitude of the steady-state current during open circuit failure of the stator winding. The proposed control method controls the magnitude and phase angle of the healthy phase current, excluding the faulty phase, to compensate for the torque ripple that occurs in the case of a phase open failure of the motor. The magnitude and phase angle of the controlled steady-state current are calculated for each phase so that copper loss increase is minimized. The proposed control method was verified using hardware-in-the-loop simulation (HILS) of a 12-phase BLDC motor. HILS verification confirmed that the increase in the loss of the stator winding and the magnitude of the torque ripple decreased compared with the open phase fault of the motor.