• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.6
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• pp.706-711
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• 2014

A low power 6-bit flash ADC that uses an input voltage range detection algorithm is described. An input voltage level detector circuit has been designed to overcome the disadvantages of the flash ADC which consume most of the dynamic power dissipation due to comparators array. In this work, four digital input voltage range detectors are employed and each input voltage range detector generates the specific clock signal only if the input voltage falls between two adjacent reference voltages applied to the detector. The specific clock signal generated by the detector is applied to turn the corresponding latched comparators on and the rest of the comparators off. This ADC consumes 68.82 mW with a single power supply of 1.2V and achieves 4.3 effective number of bits for input frequency up to 1 MHz at 500 MS/s. Therefore it results in 4.6 pJ/step of Figure of Merit (FoM). The chip is fabricated in 0.13-um CMOS process.

• The Transactions of the Korean Institute of Electrical Engineers B
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• v.53 no.1
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• pp.47-54
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• 2004

A new high voltage DC power supply is proposed. The proposed power supply is constructed with several power converters connected in series. It is easy to obtain high DC voltage for the same structure of each power converter. The output DC power of the proposed power supply can be disconnected from the load within several hundred microseconds at the instant of a load short-circuit fault. The rising time of the output DC voltage is also as small as several hundred microseconds, and there is no overshoot of the voltage because all of the output filter capacitors keep undischarged state even in load short-circuit condition. Therefore, the proposed scheme is suitable for the protection of frequent output short-circuit and fast on/off switching of output DC voltage. The proposed power supply has improved features such as simple structure, high power factor, and reduced size and volume compared with the conventional schemes. The operating principle is described and the validity of the proposed scheme is proved through simulations and experiments.

• Proceedings of the KIPE Conference
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• 2003.07a
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• pp.327-331
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• 2003

This paper proposes a novel ZVZCS-PWM Boost Converter. It enables the main switch to be turned on and off with both zero voltage and zero current and the auxiliary switch to be turned on and off with ZCS, the rectify diode to be turned on and off with ZVS. Moreover, this converter is suitable for not on]y minority carrier device but also majority carrier device. The auxiliary resonant circuit of the proposed boost converter is placed out the main power path, therefore, there are no voltage/current stresses on the main switch and diode. The operation of the proposed boost converter is explained and analyzed theoretical and experimentally, from a prototype operating at 100kHz, with an input voltage rated at 50V.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.28 no.11A
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• pp.902-911
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• 2003

Using InGaP/GaAs HBT power cells with a 2.0${\times}$20$\mu\textrm{m}$$^2$ emitter area of a unit HBT, a two stage MMIC power amplifier has been developed for IMT-2000 handsets. An active-bias circuit has been used for temperature compensation and reduction in the idling current. Fitting on measured S-parameters of the HBT cells, circuit elements of HBT's nonlinear equivalent model have been extracted. The matching circuits have been designed basically with the extracted model. A two stage HBT MMIC power amplifier fabricated using ETRI's HBT process. The power amplifier produces an 1-㏈ compressed output power(P$\_$l-㏈/) of 28.4 ㏈m with 31% power added efficiency(PAE) and 23-㏈ power gain at 1.95 GHz in on-wafer measurement. Also, the power amplifier produces a 26 ㏈m output power, 28% PAE and a 22.3-㏈ power gain with a -40 ㏈c ACPR at a 3.84 ㎒ off-center frequency in COB measurement.quency in COB measurement.

• The Transactions of the Korean Institute of Electrical Engineers
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• v.32 no.10
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• pp.335-340
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• 1983

The analysis of static power converter circuit using state-space method is presented. Semiconductors are modeled in two-state resistors depending on their ON or OFF states. Then the modes of circuit are determined according to the conducting states of semiconductors and different describing matrices are given automatically for each mode. Newton-Raphson algorithm is used as an iterative method for obtaining steady-state solution and an adjoint network is introduced for the efficient and accurate evaluation of the Jacobi matrix in the algorithm. Using the porogram exploited from the above algorithm, it is shown through examples that the results are in good agreement with the analytic solutions and computation time is considerably reduced for obtaining the steady-state solutions.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.33B no.3
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• pp.56-61
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• 1996

In this paper, new buck converter of a TV power system is presented. First, we devised a revised driving circuit for an emitter-coupled type buck converter, by which it is possible to reduce the material cost of transformers and voltage stress of power device. Secondly, we adopted a hybrid oscillation technique. When TV system is in off-stage, initial standby power which is necessary for remote controllable TV system is supplied by self-oscillating mode. Main power which is necessry in TV system bing on state is provided by an externally triggered oscillating mode. The switching frequency is synchronized to the oscillating frequency of horizontal deflection in TV, by which we can reduce picture noises and the size of power transformer. Thirdly, a simple error amplifier is inserted to the feed-back loop to keep the output voltage constant which means pulse width modulatio mode is added in driving part of power device. Finally, we showed by experiments that our proposed converter performs well enough to be close to the theoretically predicted values.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.25 no.3
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• pp.40-49
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• 2011

This paper presents novel circuit topology of half-bridge soft-switching PWM inverter type DC-DC high power converter for DC bus feeding power plants. The proposed DC-DC power converter is composed of a typical voltage source-fed, half-bridge high frequency PWM inverter with a high frequency planar transformer link PWM control scheme and parallel capacitive lossless snubbers. The operating principle of the new DC-DC converter treated here is described by using switching mode-equivalent circuits, together with its unique features. All the active power switches in the half-bridge arms and input DC bus lines can achieve ZCS turn-on and ZVS turn-off commutation transitions. The total turn-off switching losses of the power switches can be significantly reduced. As a result, high switching frequency IGBTs can actually be selected in the frequency range of 40[kHz] under the principle of soft-switching. The performance evaluations of the experimental setup are illustrated practically.

• Journal of Power Electronics
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• v.15 no.2
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• pp.366-377
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• 2015

In order to minimize switching losses for high power applications, a boost PFC rectifier with a novel passive lossless snubber circuit is proposed. The proposed lossless snubber is composed of coupled inductors merged into a boost inductor. This method compared with conventional methods does not need additional inductor cores and it reduces extra costs to implement a soft switching circuit. Especially, the proposed circuit can reduce the reverse recovery current of output diode rectifiers due to the coupling effect of the inductor. During turn-on and turn-off operating modes, the proposed PFC converter operates under soft switching conditions with high power conversion efficiency. In addition, the performance improvement and analysis of the operating effects of the coupled inductors were also presented and verified with a 3.3 kW prototype rectifier.

• Journal of Power Electronics
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• v.18 no.2
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• pp.375-382
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• 2018

A novel active controlled primary current cutting-off zero-voltage and zero-current switching (ZVZCS) PWM three-level dc-dc converter (TLC) is proposed in this paper. The proposed converter has some attractive advantages. The OFF voltage on the primary switches is only Vin/2 due to the series connected structure. The leading-leg switches can obtain zero-voltage switching (ZVS), and the lagging-leg switches can achieve zero-current switching (ZCS) in a wide load range. Two MOSFETs, referred to as cutting-off MOSFETs, with an ultra-low on-state resistance are used as active controlled primary current cutting-off components, and the added conduction loss can be neglected. The added MOSFETs are switched ON and OFF with ZCS that is irrelevant to the load current. Thus, the auxiliary switching loss can be significantly minimized. In addition, these MOSFETs are not series connected in the circuit loop of the dc input bus bar and the primary switches, which results in a low parasitic inductance. The operation principle and some relevant analyses are provided, and a 6-kW laboratory prototype is built to verify the proposed converter.

• The Transactions of the Korean Institute of Electrical Engineers B
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• v.55 no.8
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• pp.389-395
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• 2006

In the single-phase switched reluctance motor (SRM) drive, the required DC source is generally supplied by the circuit consisting of bridge rectifier with diodes and many filter capacitances connected with AC source. Although the peak torque ripple of SRM is small because of large capacity of the capacitance, the charge and discharge time swhich the AC source acts on the capacitance are small and the peak current will pass on the side of source, so power factor and system efficiency decrease. Therefore a novel SRM drive system is presented in this paper, which includes drive circuit realizing reduction of torque ripple and improvement of power factor and switching topology. The proposed drive circuit consists of one switching part and diodes which can separate the output of AC/DC rectifier from the large capacitance and supply power to SRM alternately in order to realize reduction of torque ripple and improvement of power factor through the turn on and turn off of switching part. In addition, the validity of method is tested by simulation and experiment.