Fig. 1. Active controlled primary current cutting-off ZVZCSPWM TLC.
Fig. 2. Basic operation principle.
Fig. 3. Operation stages of the proposed converter: (a) stage 1; (b) stage 2; (c) stage 3; (d) stage 4; (e) stage 5; (f) stage 6; (g) stage 7.
Fig. 4. Conventional ZVZCS TLC. (a) Diode cut-off. (b) Secondaryside active reset.
Fig. 5. Layouts of the IGBTs and lamination bus bars for: (a)proposed converter and Fig. 4(b), (b) Fig. 4(a).
Fig. 6. Control signals of S1, S3, S4 and S5.
Fig. 7. Waveform of vBC.
Fig. 8. Waveform of iP.
Fig. 9. Waveform of vCBL.
Fig. 10. Waveforms of vS5 and vS6.
Fig. 11. Waveform of vDo1.
Fig. 12. Waveform of iLo.
Fig. 13. ZCS of S5 and S6.
Fig. 14. ZCS of S3.
Fig. 15. ZVS of S1.
Fig. 16. Waveforms of vS4 and iS4.
Fig. 17. Waveforms of vS2 and iS2.
Fig. 18. Efficiency comparison results.
Fig. 19. Main power loss distribution with a 400A load current.
Fig. 20. Photo of the prototype.
TABLE I ADDED COMPONENTS, ADDED COST AND A PERFORMANCE COMPARISON
Table II MAIN PARAMETERS OF THE PROTOTYPE
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