• Proceedings of the KIEE Conference
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• 1998.07g
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• pp.2296-2298
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• 1998

In this paper, an on-chip learning pulse-mode digital neural network with a massively parallel yet compact and flexible network architecture is suggested. Algebraic neural operations are replaced by stochastic processes using pseudo-random sequences and simple logic gates are used as basic computing elements. Using Back-propagation algorithm both feed-forward and learning phases are efficiently implemented with simple logical gates. RNG architecture using LFSR and barrel shifter are adopted to avoid some correlation between pulse trains. Suggested network is designed in digital circuit and its performance is verified by computer simulation.

• ETRI Journal
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• v.31 no.2
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• pp.111-120
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• 2009

Network-on-chip (NoC) architecture provides a highper-formance communication infrastructure for system-on-chip designs. Circuit-switched networks guarantee transmission latency and throughput; hence, they are suitable for NoC architecture with real-time traffic. In this paper, we propose an efficient integrated scheme which automatically maps application tasks onto NoC tiles, establishes communication circuits, and allocates a proper bandwidth for each circuit. Simulation results show that the average waiting times of packets in a switch in $6{\times}6$6, $8{\times}8$, and $10{\times}10$ mesh NoC networks are 0.59, 0.62, and 0.61, respectively. The latency of circuits is significantly decreased. Furthermore, the buffer of a switch in NoC only needs to accommodate the data of one time slot. The cost of the switch in the circuit-switched network can be reduced using our scheme. Our design provides an effective solution for a critical step in NoC design.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.1
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• pp.166-173
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• 2013

As the number of IPs and the communication volume among them have constantly increased, on-chip crossbar network is now the most widely-used on-chip communication backbone of contemporary SoCs. The on-chip crossbar network consists of multiple crossbars and the connections among the IPs and the crossbars. As the complexity of SoCs increases, it has also become more and more complex to determine the topology of the crossbar network. To tackle this problem, this paper proposes an on-chip crossbar network topology method for application-specific systems. The proposed method uses mixed integer linear programming to solve the topology synthesis problem, thus the global optimality is guaranteed. Unlike the previous MILP-based methods which represent the topology with adjacency matrixes of IPs and crossbar switches, the proposed method uses the communication edges among IPs as the basic element of the representation. The experimental results show that the proposed MILP formulation outperforms the previous one by improving the synthesis speed by 77.1 times on average, for 4 realistic benchmarks.

• Journal of Mechanical Science and Technology
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• v.14 no.6
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• pp.622-632
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• 2000

In a high precision vertical machining center, the estimation of cutting forces is important for many reasons such as prediction of chatter vibration, surface roughness and so on. The cutting forces are difficult to predict because they are very complex and time variant. In order to predict the cutting forces of end-milling processes for various cutting conditions, their mathematical model is important and the model is based on chip load, cutting geometry, and the relationship between cutting forces and chip loads. Specific cutting force coefficients of the model have been obtained as interpolation function types by averaging forces of cutting tests. In this paper the coefficients are obtained by neural network and the results of the conventional method and those of the proposed method are compared. The results show that the neural network method gives more correct values than the function type and that in the learning stage as the omitted number of experimental data increase the average errors increase as well.

• Fire Science and Engineering
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• v.10 no.2
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• pp.28-39
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• 1996

A recently developed electro-thermal simulation methodology is used to analyze the behavior of a PWM(Pulse-Width-Modulated) voltage source inverter which uses IGBT(Insulated Gate Bipolar Transistor) as the switching devices. In the electro-thermal network simulation methdology, the simulator solves for the temperature distribution within the power semiconductor devices(IGBT electro-thermal model), control logic circuitry, the IGBT gate drivers, the thermal network component models for the power silicon chips, package, and heat sinks as well as the current and voltage within the electrical network. The thermal network describes the flow of heat form the chip surface through the package and heat sink and thus determines the evolution of the chip surface temperature used by the power semiconductor device models. The thermal component model for the device silicon chip, packages, and heat sink are developed by discretizing the nonlinear heat diffusion equation and are represented in component from so that the thermal component models for various package and heat sink can be readily connected to on another to form the thermal network.

• Proceedings of the Acoustical Society of Korea Conference
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• 1993.06a
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• pp.117-120
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• 1993

In this paper, we explore the possibility of URAN(Universally Reconstructable Artificial Neural-network) VLSI chip for speech recognition. URAN, a newly developed analog-digital hybrid neural chip, is discussed in respects to its input, output, and weight accuracy and their relations to its performance on speaker independent digit recognition. Multi-layer perceptron(MLP) nets including a large frame input layer are used to recognize a digit syllable at a forward retrieval. The simulation results using the full and limited floating precision computations for the input, output, and weight variables of the network give the comparable classification performance. An MLP with piecewise linear hidden and output units is also trained successfully using low accuracy computation.

• Journal of the Korean Institute of Intelligent Systems
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• v.10 no.3
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• pp.270-279
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• 2000

This paper describes the on-chip learning algorithm of neural networks using the stochastic pulse arithmetic. Stochastic pulse arithmetic is the computation using the numbers represented by the probability of 1' and 0's occurrences in a random pulse stream. This stochastic arithmetic has the merits when applied to neural network ; reduction of the area of the implemented hardware and getting a global solution escaping from local minima by virtue of the stochastic characteristics. And in this study, the on-chip learning algorithm is derived from the backpropagation algorithm for effective hardware implementation. We simulate the nonlinear separation problem of the some character patterns to verify the proposed learning algorithm. We also had good results after applying this algorithm to recognize printed and handwritten numbers.

• Journal of the Microelectronics and Packaging Society
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• v.24 no.3
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• pp.1-6
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• 2017

As the performance and density of IC devices increase, especially the clock frequency increases, power grid network integrity problems become more challenging. To resolve these power integrity problems, the use of passive devices such as resistor, inductor, and capacitor is very important. To manage the power integrity with little noise or ripple, decoupling capacitors are essential in electronic packaging. The decoupling capacitors are classified into voltage regulator capacitor, board capacitor, package capacitor, and on-chip capacitor. For next generation packaging technologies such as 3D packaging or wafer level packaging on-chip MIM decoupling capacitor is the key element for power distribution and delivery management. This paper reviews the use and necessity of on-chip decoupling capacitor.

• ETRI Journal
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• v.30 no.6
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• pp.783-789
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• 2008

A bio-inspired vision chip for edge detection was fabricated using 0.35 ${\mu}m$ double-poly four-metal complementary metal-oxide-semiconductor technology. It mimics the edge detection mechanism of a biological retina. This type of vision chip offer several advantages including compact size, high speed, and dense system integration. Low resolution and relatively high power consumption are common limitations of these chips because of their complex circuit structure. We have tried to overcome these problems by rearranging and simplifying their circuits. A vision chip of $160{\times}120$ pixels has been fabricated in $5{\times}5\;mm^2$ silicon die. It shows less than 10 mW of power consumption.

• JSTS:Journal of Semiconductor Technology and Science
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• v.15 no.1
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• pp.85-95
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• 2015

Network-on-chip (NoC) has evolved to overcome the issues of traditional bus-based on-chip interconnect. In NoC-reuse as TAM, the test schedulers are constrained with the topological position of cores and test access points, which may negatively affect the test time. This paper presents a scalable hybrid test data transportation scheme that allows to simultaneously test multiple heterogeneous cores of NoC-based SoCs, while reusing NoC as TAM. In the proposed test scheme, single test stimuli set of multiple CUTs is embedded into each flit of the test stimuli packets and those packets are multicast to the targeted CUTs. However, the test response packets of each CUT are unicast towards the tester. To reduce network load, a flit is filled with maximum possible test response sets before unicasting towards the tester. With the aid of Verilog and analytical simulations, the proposed scheme is proved effective and the results are compared with some recent techniques.