• 한국마이크로전자및패키징학회:학술대회논문집
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• 한국마이크로전자및패키징학회 2003년도 기술심포지움 논문집
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• pp.195-202
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• 2003

In this study, failure mechanisms of Au stud bumps/ACF flip chip joints were investigated underhigh current stressing condition. For the determination of allowable currents, I-V tests were performed on flip chip joints, and applied currents were measured as high as almost 4.2Amps $(4.42\times10^4\;Amp/cm^2)$. Degradation of flip chip joints was observed by in-situ monitoring of Au stud bumps-Al pads contact resistance. All failures, defined at infinite resistance, occurred at upward electron flow (from PCB pads to chip pads) applied bumps (UEB). However, failure did not occur at downward electron flow applied bumps (DEB). Only several $m\Omega$ contact resistance increased because of Au-Al intermetallic compound (IMC) growth. This polarity effect of Au stud bumps was different from that of solder bumps, and the mechanism was investigated by the calculation of chemical and electrical atomic flux. According to SEM and EDS results, major IMC phase was $Au_5Al_2$, and crack propagated along the interface between Au stud bump and IMC resulting in electrical failures at UEB. Therefore. failure mechanisms at Au stud bump/ACF flip chip Joint undo high current density condition are: 1) crack propagation, accompanied with Au-Al IMC growth. reduces contact area resulting in contact resistance increase; and 2) the polarity effect, depending on the direction of electrons. induces and accelerates the interfacial failure at UEBs.

• 한국생물공학회:학술대회논문집
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• 한국생물공학회 2000년도 추계학술발표대회 및 bio-venture fair
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• pp.115-118
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• 2000

미세 가공 기술을 이용하여 제작된 IDA 전극을 활용하여 임피던스 측정방식의 cell chip으로의 응용에 대해 고찰하였다. IDA 전극은 기존의 반도체 공정으로서 손쉽게 제작할 수 있고, 대량 제작시 전극의 재현성 확보가 용이하고 소형화 할 수 있으며 낮은 단가로 제작될 수 있는 장점이 있다. IDA 전극을 채용한 cell chip을 B16-F1 melanoma 세포 배양에 적용한 결과, 세포성장과 임피던스 변화량이 상관성을 보였고, 세포의 성장을 저해하는 약물의 투과시 cell chip의 임피던스 변화 역시 기존의 방법과 유사한 결과를 보여 주었다.

• 대한전기학회논문지:전기물성ㆍ응용부문C
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• 제53권12호
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• pp.589-595
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• 2004

The ESD protection characteristic of chip varistors on a circuit board can not be analyzed by using a conventional circuit simulator due to its microwave characteristic. Thus, by employing Agilent's microwave circuit simulator ADS, we showed that the ESD Protection characteristic or chip varistors can be investigated. order to got more precise simulation results, a chip varistor model was extracted from the electrical characteristic of a TDK's chip varistor and the distributed circuit based pattern was designed as the ESD propagation path. The simulation results showed that the ESD protection characteristic of a chip varistors can be improved drastically by reducing the ESD propagation path.

• 센서학회지
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• 제4권4호
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• pp.55-61
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• 1995

가변 입력전압을 이용하여 ISFET의 문턱전압을 검출하는 새로운 개념의 ISFET array chip을 설계하였다. 설계된 칩은 240개의 pH-ISFET와 신호처리회로를 포함하며, 증가된 신뢰성 및 정확성, 디지탈 출력 그리고 멀티센서로의 응용성 등의 특성을 가진다. 칩제조를 위해 CMOS 공정을 응용한 새로운 공정을 설계하였고 칩을 layout 하였다.

• Molecular & Cellular Toxicology
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• 제2권4호
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• pp.279-284
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• 2006

This paper describes the fabrication methods of a carbon nanotube (CNT) filter and a microdialysis chip. A CNT filter can help perform dialysis on a microfluidic chip. In this study, a membrane type of a CNT filter is fabricated and located in a microfluidic chip. The filter plays a role of a dialysis membrane in a microfluidic chip. In the fabrication process of a CNT filter, individual CNTs are entangled each other by amide bonding that is catalyzed by 1-Ethyl-3-(3-dimethylaminopropyl)carbodiimide (EDC) and N-hydroxysuccinimide (NHS). The chemically treated CNTs are shaped to form a CNT filter using a PDMS film-mold and vacuum filtering. Then, the CNT filter is sandwiched between PDMS substrates, and they are bonded together using a thin layer of PDMS prepolymer as adhesive. The PDMS substrates are fabricated to have a microchannel by standard photo-lithography technique.

• 한국CDE학회논문집
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• 제5권2호
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• pp.155-167
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• 2000

To be presented is two-dimensional chip-load analysis for cutting-load smoothing which is needed in unmanned machining and high speed machining of sculptured surfaces. Cutter-engagement angle and effective cutting depth are defined as chip-loads which are the geometrical measures corresponding to cutting-load while machining. The extreme values of chip-loads are geometrically derived in the line-line and line-arc-line blocks of the two-dimensional NC-codes. AFA(automatic feedrate adjustment) strategy for cutting-load smoothing is presented based on the chip-load trajectories.

• 제어로봇시스템학회논문지
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• 제8권6호
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• pp.514-523
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• 2002

Feeder arrangement is an important element of process planning for printed circuit board assembly systems. This paper newly proposes a feeder arrangement method for multihead-gantry chip mounters. The multihead-gantry chip mounters are very popular in printed circuit board assembly system, but the research has been mainly focused on single-head-gantry chip mounters. We present an integer programming formulation for optimization problem of multihead-gantry chip mounters, and propose a heuristic method to solve the large NP-complete problem in reasonable time. Dynamic programming method is then applied to feeder arrangement optimization to reduce the overall assembly time. Comparative simulation results are finally presented to verify the usefulness of the proposed method.

• 센서학회지
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• 제20권3호
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• pp.162-167
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• 2011

In this paper, we propose a vision system using a field programmable gate array(FPGA) and a smart vision chip. The output of the vision chip is varied by illumination conditions. This chip is suitable as a surveillance system in a dynamic environment. However, because the output swing of a smart vision chip is too small to definitely confirm the warning signal with the FPGA, a modification was needed for a reliable signal. The proposed system is based on a transmission control protocol/internet protocol(TCP/IP) that enables monitoring from a remote place. The warning signal indicates that some objects are too near.

• 한국지하수토양환경학회:학술대회논문집
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• 한국지하수토양환경학회 2004년도 임시총회 및 추계학술발표회
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• pp.231-234
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• 2004

The experiments on some organic materials used in SAPS are carried out for the better sulfate reduction efficiency and the longer lifetime. Organic materials include spent mushroom compost, sewage sludge, oak chip compost and the combination of there. Reactors with mushroom compost, sewage sludge, the mixture of mushroom compost and sewage sludge, and the mixture of mushroom compost and oak chip compost maintained pH higher than 6.0. Reactors with mushroom compost, the mixture of mushroom compost and sewage sludge, and the mixture of mushroom compost and oak chip compost maintained reduction condition. Reactors with sewage sludge, oak chip compost and the mixture of sewage and oak chip compost produced COD less than 2,000ppm. Reactors with sewage and the mixture of mushroom compost, sewage sludge, oak chip compost showed about 60% of sulfate removal ratios.

• KSBB Journal
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• 제18권5호
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• pp.429-433
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• 2003

LAL 측정용 chip을 제작하기 위해서 우선 시료의 부피 감소에 대한 비탁법과 비색법을 비교하였다. 비색법은 낮은 부피에서 높은 감도를 보여 주었으며 시료의 부피와 무관하게 같은 endotoxin의 농도에서는 같은 흡광도를 보인다는 결론을 얻었다. Endotoxin의 농도에 따른 표준곡선을 end point법과 kinetic point법을 비교한 결과 대한약전의 기준에 적합한 kinetic point법이 적합하였다. 이러한 기초 실험결과를 통해 PDMS LOC를 제작하여 LAL 시험을 수행하였다. LOC를 이용하여 더 짧은 시간과 더 작은 시료로 시험이 가능하도록 하였다. 특히 PDMS LOC는 복잡한 channel을 쉽게 만들 수 있을 뿐 아니라 mold를 이용하여 상용화를 위한 대량 생산이 가능하다. 따라서 PDMS를 이용한 LOC의 제작과 실험을 통해 기존의 수작업의 LAL 시험을 LOC를 이용한 다중시료 측정과 자동화의 가능성을 제시하였다.