• Proceedings of the KIEE Conference
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• 1993.11a
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• pp.335-337
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• 1993

Offset voltage and drift characteristics of operational amplifier are critical factor to precision AID conversion System. In this study, a method is suggested to design the programmable A/D conversion system which has high resolution and low drift characteristics. First, hardware was designed to reduce the offset voltage of integrator and comparator, and analog switches are connected to reduce the drift characteristics of operational amplifier. And then, a calibration software technique was performed to obtain the stable data from A/D converter. The main advantage of our method is high precision A/D converter can be constructed with low cost and high confidence. Therefore proposed method is expected to be used in the industrial field where a high precision measurement is required.

• ETRI Journal
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• v.34 no.4
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• pp.518-526
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• 2012

This paper proposes LC voltage-controlled oscillator (VCO) phase-locked loop (PLL) and ring-VCO PLL topologies with low-phase noise. Differential control loops are used for the PLL locking through a symmetrical transformer-resonator or bilaterally controlled varactor pair. A differential compensation mechanism suppresses out-band spurious tones. The prototypes of the proposed PLL are implemented in a CMOS 65-nm or 45-nm process. The measured results of the LC-VCO PLL show operation frequencies of 3.5 GHz to 5.6 GHz, a phase noise of -118 dBc/Hz at a 1 MHz offset, and a spur rejection of 66 dBc, while dissipating 3.2 mA at a 1 V supply. The ring-VCO PLL shows a phase noise of -95 dBc/Hz at a 1 MHz offset, operation frequencies of 1.2 GHz to 2.04 GHz, and a spur rejection of 59 dBc, while dissipating 5.4 mA at a 1.1 V supply.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.9 no.6
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• pp.843-849
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• 1998

A voltage controlled oscillator using dielectric resonator for 2.4 GHz WLL System is designed and fabricated. To improve the phase noise characteristic resonator is used as an inductor of VCO. At the bias condition of 5 V and 10 mA, the output power and phase noise in the operating frequency range of 2210~2240 MHz are 0 dBm and 100 dBc/Hz 10 kHz offset from the carrier, respectively. The phase noise and harmonic response of fabricated VCO are suitable for WLL system.

• Proceedings of the KIPE Conference
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• 2005.07a
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• pp.584-586
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• 2005

The stroke of piston in the linear compressor driven by LPMSM can be obtained from integrating the input voltage and current of LPMSM, and may be diverged due to dc components In the voltage and current. The strategy to prevent the divergence of stroke using both the high-pass filter and dc offset compensation was suggested. The equations for the magnitude and phase of the stroke and also dc offset including the stroke are derived as a function of the cut-off frequency of HPF. The performance of stroke calculation scheme has been verified by experimentally on a linear compressor drive system, where the control was implemented by a 16-bit DSP.

• Proceedings of the KIEE Conference
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• 1998.11c
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• pp.959-961
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• 1998

In this paper, we present design rule of high-voltage rectangular generator working in wide band frequency domain. Though power electronics now have voltage ratings up to several kV, it is difficult to design and fabricate high-voltage systems with the power electronic devices alone. So we have combined IGBT with technically designed transformer to get the high-voltage rectangular waveforms. In this work, next two things are the main factors. The first one is design of transformer working low-frequency domain of less than 10Hz. And the second one is adding offset voltage part. As a result, we can get variable frequency high-voltage rectangular waveform and this can be used as a voltage source of sandpaper manufacturing process.

• Journal of IKEEE
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• v.3 no.2 s.5
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• pp.161-167
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• 1999

3-input neuron-MOSFET inverters and 3-bit D/A converters using enhancement type device have been designed and fabricated by using standard 2-poly CMOS process. The voltage transfer curve and the noise margin of neuron-MOSFET inverters have been measured and characterized as the same method in normal CMOS inverters. From the theoretical calculation of the effects of coupling ratio on the voltage transfer curve and noise margin, we set up the design guideline for the gate oxide thickness and input gate layout in neuron-MOSFET inverters. BT using one of input gates as a control gate, we can design and fabricate the neuron-MOSFET D/A converter without offset voltage.

• JSTS:Journal of Semiconductor Technology and Science
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• v.9 no.3
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• pp.160-165
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• 2009

A 12b 2 MS/s cyclic ADC processing 3.3 Vpp single-ended rail-to-rail input signals is presented. The proposed ADC demonstrates an offset voltage less than 1 mV without well-known calibration and trimming techniques although power supplies are directly employed as voltage references. The SHA-free input sampling scheme and the two-stage switched op-amp discussed in this work reduce power dissipation, while the comparators based on capacitor-divided voltage references show a matched full-scale performance between two flash sub ADCs. The prototype ADC in a $0.18{\mu}m$ 1P6M CMOS demonstrates the effective number of bits of 11.48 for a 100 kHz full-scale input at 2 MS/s. The ADC with an active die area of $0.12\;mm^2$ consumes 3.6 m W at 2 MS/s and 3.3 V (analog)/1.8 V (digital).

• Journal of Power Electronics
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• v.15 no.4
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• pp.974-986
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• 2015

A novel inverter fault-tolerant control scheme is proposed to drive brushless DC motor. A fault-tolerant inverter and its three fault-tolerant schemes (i.e., phase A fault-tolerant, phase B fault-tolerant, and phase C fault-tolerant) are analyzed. Eight voltage vectors are summarized and a voltage vector selection table is used in the control scheme to improve the midpoint current of the split capacitors. A stator flux observer is proposed. The observer can improve flux estimation, which does not require any speed adaptation mechanism and is immune to speed estimation error. Global stability of the flux observer is guaranteed by the Lyapunov stability analysis. A novel stator resistance estimator is incorporated into the sensorless drive to compensate for the effects of stator resistance variation. DC offset effects are mitigated by introducing an integral component in the observer gains. Finally, a control system based on the control scheme is established. Simulation and experiment results show that the method is correct and feasible.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.5
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• pp.152-159
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• 2016

This paper describes an offset and 1/f noise cancellation technique based hall sensor signal processor. The hall sensor outputs a hall voltage from the input magnetic field, which direction is orthogonal to hall plate. The two major elements to complete the hall sensor operation are: the one is a hall sensor to generate hall voltage from input magentic field, and the other one is a hall signal process system to cancel the offset and 1/f noise of hall signal. The proposed hall sensor splits the hall signal and unwanted signals(i.e. offset and 1/f noise) using a spinning current biasing technique and chopper stabilizer. The hall signal converted to 100 kHz and unwanted signals stay around DC frequency pass through chopper stabilizer. The unwanted signals are bloked by highpass filter which, 60 kHz cut off freqyency. Therefore only pure hall signal is enter the ADC(analog to dogital converter) for digitalize. The hall signal and unwanted signal at the output of an amplifer and highpass filter, which increase the power level of hall signal and cancel the unwanted signals are -53.9 dBm @ 100 kHz and -101.3 dBm @ 10 kHz. The ADC output of hall sensor signal process system has -5.0 dBm hall signal at 100 kHz frequency and -55.0 dBm unwanted signals at 10 kHz frequency.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.49 no.8
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• pp.41-46
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• 2012

A quadrature voltage controlled oscillator(QVCO) for X-band is presented in this paper. The QVCO has fabricated in Charted $0.13{\mu}m$ CMOS process. The QVCO consists of two cross-coupled differential VCO and two differential buffers. The QVCO is controlled by 4 bit of capacitor bank and control voltage of varactor. To have a linear quality factor of varactors, voltage biases of varactors are difference. The QVCO generates frequency tuning range from 6.591 GHz to 8.012 GHz. The phase noise is -101.04 dBc/Hz at 1MHz Offset when output frequency is 7.150 GHz. The supply voltage is 1.5 V and core current 6.5-8.5 mA.