• Proceedings of the IEEK Conference
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• 2008.06a
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• pp.455-456
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• 2008

New CMOS ROM cell is reported in this paper, distinguished from conventional ones in that it can be re-programmed by multi-times. It uses the comparator offset as the physical storage quantity and the MOSFET FN stress effect for offset programming. It demands very low offset for read, and works well in very low voltage. It can become a promising ROM solution for various SoC systems.

• The Transactions of the Korean Institute of Power Electronics
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• v.3 no.4
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• pp.280-286
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• 1998

This paper proposes a novel method to reduce the torque ripple due to the non-ideality of the current sensing parts in vector-controlled inverter-fed AC motor drive systems. For PMSM(Permanent Magnet Synchronous Motor), motor output torque equations are derived in terms of their offset voltages and different voltage transducing gains. And the effects of phase current errors on motor torque are analyzed for both salient PMSM and non-salient PMSM. The proposed method can eliminate the torque ripple by nulling the offset voltages and setting the voltage transducing gains to the same value. To verify the proposed method, digital simulations are carried out for non-salient PMSM.

• The Transactions of the Korean Institute of Power Electronics
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• v.20 no.3
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• pp.201-208
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• 2015

The effects of dead-time and offset error, which cause output current distortion in single-phase grid-connected inverters are investigated this paper. Offset error is typically generated by measuring phase current, including the voltage unbalance of analog devices and non-ideal characteristics in current measurement paths. Dead-time inevitably occurs during generation of the gate signal for controlling power semiconductor switches. Hence, the performance of the grid-connected inverter is significantly degraded because of the current ripples. The current and voltage, including ripple components on the synchronous reference frame and stationary reference frame, are analyzed in detail. An algorithm, which has the proportional resonant controller, is also proposed to reduce current ripple components in the synchronous PI current regulator. As a result, computational complexity of the proposed algorithm is greatly simplified, and the magnitude of the current ripples is significantly decreased. The simulation and experimental results are presented to verify the usefulness of the proposed current ripple reduction algorithm.

• Journal of electromagnetic engineering and science
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• v.17 no.2
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• pp.98-104
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• 2017

This work describes the development and comparison of two phase-locked loops (PLLs) based on a 65-nm CMOS technology. The PLLs incorporate two different topologies for the output voltage-controlled oscillator (VCO): LC cross-coupled and differential Colpitts. The measured locking ranges of the LC cross-coupled VCO-based phase-locked loop (PLL1) and the Colpitts VCO-based phase-locked loop (PLL2) are 119.84-122.61 GHz and 126.53-129.29 GHz, respectively. Th e output powers of PLL1 and PLL2 are -8.6 dBm and -10.5 dBm with DC power consumptions of 127.3 mW and 142.8 mW, respectively. Th e measured phase noise of PLL1 is -59.2 at 10 kHz offset and -104.5 at 10 MHz offset, and the phase noise of PLL2 is -60.9 dBc/Hz at 10 kHz offset and -104.4 dBc/Hz at 10 MHz offset. The chip sizes are $1,080{\mu}m{\times}760{\mu}m$ (PLL1) and $1,100{\mu}m{\times}800{\mu}m$ (PLL2), including the probing pads.

• The Transactions of the Korean Institute of Electrical Engineers P
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• v.64 no.2
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• pp.67-73
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• 2015

Distance relay is widely used for the protection of long transmission line. Most of distance relay used to calculate line impedance by measuring voltage and current using DFT. So if there is a computation error due to the influence of phasor by DC offset component, due to excessive vibration by measuring line impedance, overreach or underreach can be occurs, and then abnormal and non-operation of distance relay can be issue. It is very important to implement the robust distance relaying that is not affected by DC offset component. This paper describes an enhanced distance relaying based on the DC offset elimination filter to minimize the effects of DC offset on a long transmission line. The proposed DC offset elimination filter has not need any prior information. The phase angle delay of the proposed DC offset filter did not occurred and the gain error was not found. The enhanced distance relay uses fault current as well as residual current. The behavior of the proposed distance relaying using off-line simulation has been verified using data about several fault conditions generated by the ATP simulation software.

• International journal of advanced smart convergence
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• v.10 no.1
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• pp.12-23
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• 2021

This paper proposes a low power radio frequency receiver front-end where, in a single stage, single-balanced mixer and voltage-controlled oscillator are stacked on top of low noise amplifier and re-use the dc current to reduce the power consumption. In the proposed topology, the voltage-controlled oscillator itself plays the dual role of oscillator and mixer by exploiting a series inductor-capacitor network. Using a 65 nm complementary metal oxide semiconductor technology, the proposed radio frequency front-end is designed and simulated. Oscillating at around 2.4 GHz frequency band, the voltage-controlled oscillator of the proposed radio frequency front-end achieves the phase noise of -72 dBc/Hz, -93 dBc/Hz, and -113 dBc/Hz at 10KHz, 100KHz, and 1 MHz offset frequency, respectively. The simulated voltage conversion gain is about 25 dB. The double-side band noise figure is -14.2 dB, -8.8 dB, and -7.3 dB at 100 KHz, 1 MHz and 10 MHz offset. The radio frequency front-end consumes only 96 ㎼ dc power from a 1-V supply.

• Proceedings of the KIEE Conference
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• 1992.07a
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• pp.59-62
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• 1992

Power system fault transient signals are highly distorted due to the presence of high frequency components in the voltage and current signals and an exponentially decaying dc-offset component in the current signals. Modern protective relays have to make reliable fast decisions about the nature of a fault in the presence of such transients. To use a dc-offset removing filter makes relay algorithms much fast and reliable for detecting a fault. In this paper, several dc-offset removing filters are described, and characteristics of them are compared.

• Proceedings of the KIEE Conference
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• 1995.07c
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• pp.1085-1087
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• 1995

A large leakage current may be one of the critical issues for poly-silicon thin film transistors(poly-Si TFTs) for LCD applications. In order to reduce the leakage current of poly-Si TFTs, several offset gated structures have been reported. However, those devices, where the offset length in the source region is not same as that in the drain region, exhibit the asymmetric electrical performances such as the threshold voltage shift and the variation of the subthreshold slope. The different offset length is caused by the additional mask step for the conventional offset structures. Also the self-aligned implantation may not be applicable due to the mis-alignment problem. In this paper, we propose a new fabrication method for poly-Si TFTs with a self-aligned offset gated structure by employing a photo resistor reflow process. Compared with the conventional poly-Si TFTs, the device is consist of two gate electrodes, of which one is the entitled main gate where the gate bias is employed and the other is the entitled subgate which is separate from both sides of the main gate. The poly-Si channel layer below the offset oxide is protected from the injected ion impurities for the source/drain implantation and acts as an offset region of the proposed device. The key feature of our new device is the offset lesion due to the offset oxide. Our experimental results show that the offset region, due to the photo resistor reflow process, has been successfully obtained in order to fabricate the offset gated poly-Si TFTs. The advantages of the proposed device are that the offset length in the source region is the same as that in the drain region because of the self-aligned implantation and the proposed device does not require any additional mask process step.

• The Transactions of the Korean Institute of Power Electronics
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• v.22 no.1
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• pp.67-74
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• 2017

This study proposes a novel random pulse-width modulation (PWM) technique with a constant switching frequency utilizing a random offset voltage. The proposed PWM technique spreads switching harmonics by varying the position of an active voltage vector without a switching frequency variation. The implementation of the proposed PWM technique is simple because it does not require additional hardware and complex algorithm. The proposed random PWM technique is compared with the conventional PWM technique on the factors of harmonic spectrum, total harmonic distortion, and harmonic spread factor to confirm the harmonic spread effect. The validity of the proposed method is verified by simulations and experiments on a three-phase inverter drive system.

• Journal of the Korean Society of Manufacturing Process Engineers
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• v.4 no.3
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• pp.5-12
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• 2005

In wire discharge machining which is using STD 11 as die materials, the major factors of machining speed are discharge voltage, discharge current, and discharge time. All of the three factors give the effect. Increasing of the discharge pulse time gets groove width wider and it relatively increases surface roughness and clearance. If no load voltage is decreased, surface roughness is good but it decreases machining speed. If on time is increased, machining speed will get faster and clearance and offset value also get bigger.