• Journal of the Semiconductor & Display Technology
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• v.14 no.4
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• pp.72-77
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• 2015

Three-level diode clamped multilevel inverter, generally known as neutral point clamped (NPC) inverter, has an inherent problem causing neutral point (NP) potential variation. Until now, the NP potential problem of variation has been investigated and lots of solutions have also been proposed. This paper presents a neutral point voltage control technology using the anti-windup PI controller and offset technology of PWM (Pulse Width Modulation) to control the variation of NPC 3-phase three-level inverter neutral point voltage. And the proposed algorithm is tested and verified using a PLL (Phase Locked Loop) in order to synchronize the phase voltage from the line voltage of grid. It significantly improves the voltage balancing under a solar fluctuation conditions of the inverter. Experimental results show the good performance and effectiveness of the proposed method.

• Journal of the Korean institute of surface engineering
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• v.53 no.5
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• pp.207-212
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• 2020

Silver is an inexpensive precious metal and is used in various jewelry in Asia. Although silver has high potential, it has corrosion resistance that is vulnerable to boiling sulfuric acid and nitric acid. So, silver research is needed to prevent the corrosion with environment. But silver corrosion is not studied. sulfuric acid make the uniform corrosion and chloride ion make the pitting corrosion. ICCP inhibits the corrosion because it offset electrons. This study used a potential from - 4 V to 4 V to check the effect of potential. Corrosion rate is lowet at -1 V.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.12 s.354
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• pp.55-64
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• 2006

This work proposes a calibration-free 14b 70MS/s 0.13um CMOS ADC for high-performance integrated systems such as WLAN and high-definition video systems simultaneously requiring high resolution, low power, and small size at high speed. The proposed ADC employs signal insensitive 3-D fully symmetric layout techniques in two MDACs for high matching accuracy without any calibration. A three-stage pipeline architecture minimizes power consumption and chip area at the target resolution and sampling rate. The input SHA with a controlled trans-conductance ratio of two amplifier stages simultaneously achieves high gain and high phase margin with gate-bootstrapped sampling switches for 14b input accuracy at the Nyquist frequency. A back-end sub-ranging flash ADC with open-loop offset cancellation and interpolation achieves 6b accuracy at 70MS/s. Low-noise current and voltage references are employed on chip with optional off-chip reference voltages. The prototype ADC implemented in a 0.13um CMOS is based on a 0.35um minimum channel length for 2.5V applications. The measured DNL and INL are within 0.65LSB and l.80LSB, respectively. The prototype ADC shows maximum SNDR and SFDR of 66dB and 81dB and a power consumption of 235mW at 70MS/s. The active die area is $3.3mm^2$.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.44 no.12
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• pp.16-21
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• 2007

In this paper, the dual-band voltage-controled oscillator (VCO) using the composite right/left-handed (CRLH) transmission line (TL) and the tunable negative resistance based on the fin diode is presented. It is demonstrated that the CRLH TL can lead to metamaterial transmission line with the dual-band tuning capability. The dual-band operation of the CRLH TL is achieved by the frequency offset and the phase slope of the CRLH TL, and the frequency ratio of the two operating frequencies can be a non-integer. Each frequency band of VCO has to operate independently, so we have used the tunable negative resistance based on the pin diode. When the forward bias has been into the pin diode, the phase noise of VCO is $-108.34\sim-106.67$ dBc/Hz @ 100 kHz in the tuning range, $2.423\sim2.597$ GHz, whereas when the reverse bias has been fed into the pin diode, that of VCO is $-114.16\sim-113.33$ dBc/Hz @ 100 kHz in the tuning range, $5.137\sim5.354$ GHz.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.9 s.351
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• pp.10-16
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• 2006

This paper presents a fast switching CMOS frequency synthesizer with a new coarse tuning scheme for PHS applications. The proposed coarse tuning method selects the optimal tuning capacitances of the LC-VCO to optimize the phase noise and the lock-time. The measured lock-time is about $20{\mu}s$ and the phase noise is -121dBc/Hz at 600kHz offset. This chip is fabricated with $0.25{\mu}m$ CMOS technology, and the die area is $0.7mm{\times}2.1mm$. The power consumption is 54mW at 2.7V supply voltage.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.11 no.10
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• pp.3866-3872
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• 2010

This paper presents a design of high power oscillator using a spiral resonator and high power transistor with measurement. Even lots of drawbacks are known in design of oscillators using high power transistors, the spiral resonator is adopted because it has relatively high Q out of planar resonators. The designed power oscillator at 1.8GHz is fabricated and tested. Measurement shows the obtained output power is 23.5dBm at 1.74GHz with -146.76dBc/Hz of phase noise at 1MHz offset. In addition, it is illustrated that the frequency stability is excellent with the shift less than 1MHz and the measured maximum output power is around 24dBm when the bias voltages are adjusted.

• Journal of the Institute of Electronics Engineers of Korea TE
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• v.37 no.2
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• pp.69-74
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• 2000

The bandwidth of microstrip slot antenna with T-shaped feed line was a wider than one of the conventional feeding structure. When the slot antenna with bi-directional radiator wants to radiate only one direction, the reflector must be set up seperately. But this antenna doesn't need set up reflector. And then we proposed to a new method of a directional slot radiator with a cross-shaped feedline including the reflector using 2-layers dielectric materials. It is calculated waves and electric field distribution in the time domain by using FDTD method. We also are calculated return loss, VSWR, input impedance, and radiation pattern in the frequency domain by Fourier transforming the time domain results, respectively. It was found that the bandwidth of this antenna changes as length($\I_s$) and width($\W_s$) of slot, length of the horizontal feedline($\I_d$), length of the vertical feedline($\I_u$) and offset sensitively. After optimizing the parameters of design, the maximum bandwidth was measured as 1,850MHz at the center frequency 2.5 GHz.

• Journal of Sensor Science and Technology
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• v.1 no.2
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• pp.131-145
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• 1992

This paper has been described a process technology for the fabrication of Si-on-insulator(SOI) transducers and circuits. The technology utilizes Si-wafer direct bonding(SDB) and mechanical-chemical(M-C) local polishing to create a SOI structure with a high-qualify, uniformly thin layer of single-crystal Si. The electrical and piezoresistive properties of the resultant thin SOI films have been investigated by SOI MOSFET's and cantilever beams, and confirmed comparable to those of bulk Si. Two kinds of pressure transducers using a SOI structure have been proposed. The shifts in sensitivity and offset voltage of the implemented pressure transducers using interfacial $SiO_{2}$ films as the dielectrical isolation layer of piezoresistors were less than -0.2% and +0.15%, respectively, in the temperature range from $-20^{\circ}C$ to $+350^{\circ}C$. In the case of pressure transducers using interfacial $SiO_{2}$ films as an etch-stop layer during the fabrication of thin Si membranes, the pressure sensitivity variation can be controlled to within a standard deviation of ${\pm}2.3%$ from wafer to wafer. From these results, the developed SDB process and the resultant SOI films will offer significant advantages in the fabrication of integrated microtransducers and circuits.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.18 no.2 s.117
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• pp.213-218
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• 2007

In this paper, we propose the design and fabrication on high frequency CMOS VCO for DS-UWB(Direct-Sequence Ultra-WideBand) applications using 0.18 ${\mu}m$ process. The complementary cross-coupled LC oscillator architecture which is composed of PMOS, NMOS symmetrically, is designed for improving the phase noise characteristic. The resistor is used instead of current source that reduce the 1/f noise of current source. The high-speed buffer is needed for measuring the output characteristic of VCO using spectrum analyzer, therefore the high-speed inverter buffer is designed with VCO. A fabricated core VCO size is $340{\mu}m{\times}535{\mu}m$. The VCO is tunable between 7.09 and 7.52 GHz and has a phase noise lower than -107 dBc/Hz at 1-MHz offset over entire tuning range. The measured harmonic suppression is 32 dB. The VCO core circuit draws 2.0 mA from a 1.8 V supply.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.15 no.4
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• pp.335-344
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• 2004

A low phase noise EQM(Engineering Qualified Model) LO(Local Oscillator) has been developed for Ka-band satellite transponder. A VCDRO(Voltage Controlled Dielectric Resonator Oscillator) is also designed using a high impedance inverter coupled with dielectric resonator to improve the phase noise performances out of the loop bandwidth. The mechanical analysis fur housing and the thermal analysis fur circuit board are achieved. This EQM LO is applied to Ka-band satellite transponder of EQM level after environmental experiments for space application. The LO has the harmonic suppression characteristics above 52 ㏈c and requires low power consumption under 1.3 watts. The phase noise characteristics are exhibited as -101.33 ㏈c/㎐ at 10 ㎑ offset frequency and -114.33 ㏈c/㎐ at 100 ㎑ offset frequency, with the output power of 14.0 ㏈m${\pm}$0.17 ㏈ over the temperature range of -15∼＋65$^{\circ}C$.