• 대한전자공학회논문지TC
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• 제46권2호
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• pp.141-146
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• 2009

본 논문에서는 새로운 고조파 조절 회로를 이용한 Si LDMOSFET 고효율 전력증폭기를 구현하였다. 본 고조파 조절 회로는 2차, 3차 고조파 성분에 대하여 단락 임피던스를 갖으며, 입출력 정합 회로를 설계하기 위하여 사용된다. 제안된 고조파 조절 회로의 효율 개선 효과가 class-F 혹은 inverse class-F 고조파 조절 회로 보다 우수하다는 것을 증명하였다. 또한, 고조파 조절 회로가 출력 정합 회로뿐만 아니라, 입력 정합 회로에도 사용될 경우, 제안된 전력증폭기의 효율은 더욱 더 개선된다. 제안된 전력증폭기의 최대 전력 효율 (PAE)의 측정값은 1.71 GHz의 주파수 대역에서 82.68%이다. Class-F와 inverse class-F 전력증폭기와 비교할 때, 제안된 전력증폭기의 최대 PAE 측정값은 $5.08\;{\sim}\;9.91\;%$ 향상된다.

• 대한전자공학회논문지TC
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• 제47권1호
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• pp.84-90
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• 2010

본 논문에서는 주파수 조절 범위의 감소 없이 위상 잡음을 줄이고 회로 크기를 최소화하기 위하여 혼합 우좌향 전송 선로 기반의 고조파 조절 회로를 이용한 새로운 전압 제어 발진기를 제안하였다. 위상 잡음은 2차와 3차 고조파에서 동시에 단락임피던스를 갖는 새로운 고조파 조절 회로에 의해 줄어들었다. 제안된 고조파 조절 회로는 혼합 우좌향 전송 선로의 주파수 오프셋과 위상 기울기에 의한 이중 대역 특성을 갖는 혼합 우좌향 전송 선로를 이용하여 설계되었다. 높은 Q 특성의 공진기는 위상 잡음을 줄이기 위하여 사용되어 왔지만, 주파수 조절 범위가 감소하는 문제를 갖고 있다. 하지만 제안된 전압 제어 발진기의 주파수 조절 범위는 위상 잡음이 높은 Q 특성의 공진기 없이 감소하였기 때문에 줄어들지 않았다. 또한, 일반적인 우향 전송 선로 대신 혼합 우좌향 전송 선로를 이용하는 것을 통하여 회로의 크기를 소형화 하였다. 전압 제어 발진기의 위상 잡음은 5.731 ~ 5.938 GHz의 주파수 조절 범위 내에서 100 kHz의 오프셋 주파수에서 -119.17 ~ -117.50 dBc/Hz이다.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2004년도 전력전자학술대회 논문집(2)
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• pp.587-591
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• 2004

This paper proposes a novel current compensation technique that can eliminate the harmonic currents included in line currents without computation of harmonic current components. A current controller with fast dynamics for an active filter is described. Harmonic currents are directly controlled without the need for sensing and computing the harmonic current of the load current, thus simplifying the control system. Current compensation is done in the time domain, allowing a fast time response. The DC voltage control loop keeps the voltage across the DC capacitor constant. High power factor control by an active filter is described. All control functions are implemented in software using a single-chip microcontroller, thus simplifying the control circuit. Any current-controlled synchronous rectifier can be used as a shunt active filter through only the simple modification of the software and the addition of current sensors. It is shown through experimental results that the proposed controller gives good performance for the shunt active filter.

• 대한전자공학회논문지TC
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• 제45권2호
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• pp.137-144
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• 2008

본 논문에서는 위상 잡음 특성을 개선하기 위하여 고조파 조절 회로를 기반으로 한 출력 정합 회로를 이용한 전압 제어 발진기를 제안하였다. 위상 잡음은 2차, 3차 고조파 모두에서 단락 임피던스를 갖는 고조파 조절 회로를 통하여 억제되었으며, 출력 정합 회로에 연결되었다. 또한 전압 제어 발진기의 위상 잡음 특성을 더욱 더 개선하기 위하여 마이크로스트립 사각 개방 루프 다중 SRR를 이용하였다. 위상 잡음 특성 개선을 위하여 높은 Q값을 갖는 공진기 대신에 고조파 조절 회로를 기반으로 한 출력 정합 회로를 이용하였기 때문에 낮은 Q값을 갖는 공진기를 통하여 넓은 주파수 조절 범위를 얻을 수 있다. 고조파 조절 회로를 기반으로 한 출력 정합 회로와 마이크로스트립 사각 개방 루프 다중 SRR를 이용한 제안된 전압 제업 발진기의 위상 잡음 특성은 주파수 조절 범위, $5.744{\sim}5.839$ GHz에서 $-127.5{\sim}-126.33$ dBc/Hz @ 100 kHz이다. 고조파 조절 회로가 없는 출력 정합 회로와 마이크로스트립 선로 공진기를 이용한 전압 제어 발진기와 비교했을 경우, 제안된 전압 제어 발진기의 위상 잡음 특성은 26.66 dB 개선되었다.

• Journal of Power Electronics
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• 제16권5호
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• pp.1661-1668
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• 2016

A fixed off-time controlled high power factor ac-dc LED driver is proposed in this paper, which employs a novel zero-crossing-compensation (ZCC) circuit based on a fixed off-time controlled scheme. Due to the parasitic parameters of the system, the practical waveforms have a dead region. By detecting the zero-crossing boundary, the proposed ZCC circuit compensates the control signal VCOMP within the dead region, and is invalid above this region. With further optimization of the parameters KR and Kτ of the ZCC circuit, the dead zone can be eliminated and lower THD is achieved. Finally, the chip is implemented in HHNEC 0.5μm 5V/40V HVCMOS process, and a prototype circuit, delivering 7~12W of power to several 3-W LED loads, is tested under AC input voltage ranging from 85V to 265V. The test results indicate that the average total harmonic distortion (THD) of the entire system is approximately 10%, with a minimum of 5.5%, and that the power factor is above 0.955, with a maximum of 0.999.

• Journal of Power Electronics
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• 제12권5호
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• pp.800-812
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• 2012

This paper analyses the mathematical model and control strategies of a Hybrid Active Power Filter with Injection Circuit (IHAPF). The control strategy based on the load harmonic current detection is selected. A novel control method for a IHAPF, which is based on the analyzed control mathematical model, is proposed. It consists of two closed-control loops. The upper closed-control loop consists of a single fuzzy logic controller and the IHAPF model, while the lower closed-control loop is composed of an Adaptive Network based Fuzzy Inference System (ANFIS) controller, a Neural Generalized Predictive (NGP) regulator and the IHAPF model. The purpose of the lower closed-control loop is to improve the performance of the upper closed-control loop. When compared to other control methods, the simulation and experimental results show that the proposed control method has the advantages of a shorter response time, good online control and very effective harmonics reduction.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2002년도 하계학술대회 논문집 Vol.3 No.2
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• pp.1093-1096
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• 2002

In this paper, a novel multi voltage inverter system is proposed for reductions of harmonics, which can compensate reactive power. At first, we remove capacitor at input side for reactive power compensation. Secondly, by adding DC voltage to the filter capacitor, it can control power factors as lead-phase according to alterations of loads at power reception. Thirdly, if winding and single phase-bridge inverter(auxiliary circuit) is installed to DC power for reduction of harmonic, waveform of output voltages become to 36-steps. Thus, SVC(static var compensator) systems which can reduce harmonics are designed.

• Journal of Power Electronics
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• 제14권1호
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• pp.48-60
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• 2014

Multilevel inverters have been widely used for high-voltage and high-power applications. Their performance is greatly superior to that of conventional two-level inverters due to their reduced total harmonic distortion (THD), lower switch ratings, lower electromagnetic interference, and higher dc link voltages. However, they have some disadvantages such as an increased number of components, a complex pulse width modulation control method, and a voltage-balancing problem. In this paper, a novel nine-level reduced switch cascaded multilevel inverter based on a multilevel DC link (MLDCL) inverter topology with reduced switching components is proposed to improve the multilevel inverter performance by compensating the above mentioned disadvantages. This topology requires fewer components when compared to diode clamped, flying capacitor and cascaded inverters and it requires fewer carrier signals and gate drives. Therefore, the overall cost and circuit complexity are greatly reduced. This paper presents modulation methods by a novel reference and multicarrier based PWM schemes for reduced switch cascaded multilevel inverters (RSCMLI). It also compares the performance of the proposed scheme with that of conventional cascaded multilevel inverters (CCMLI). Simulation results from MATLAB/SIMULINK are presented to verify the performance of the nine-level RSCMLI. Finally, a prototype of the nine-level RSCMLI topology is built and tested to show the performance of the inverter through experimental results.

• Journal of Power Electronics
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• 제11권4호
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• pp.490-498
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• 2011

This paper presents a novel analysis, design, and implementation of a battery charging three-phase high frequency semi-controlled power converter feasible for plug-in hybrid electric vehicles. The main advantages of the proposed topology include high efficiency; due to lower power losses and reduced number of switching elements, high output power density realization, and reduced passive component ratings proportionally to the frequency. Additional advantages also include grid economic utilization by insuring unity power factor operation under different possible conditions and robustness since short-circuit through a leg is not possible. A high but acceptable total harmonic distortion of the generator currents is introduced in the proposed topology which can be viewed as a minor disadvantage when compared to traditional boost rectifiers. A hysteresis control algorithm is proposed to achieve lower current harmonic distortion for the rectifier operation. The rectifier topology concept, the principle of operation, and control scheme are presented. Additionally, a dc-dc converter is also employed in the rectifier-battery connection. Test results on 50-kHz power converter system are presented and discussed to confirm the effectiveness of the proposed topology for PHEV applications.

• 대한전기학회논문지:전기기기및에너지변환시스템부문B
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• 제54권4호
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• pp.195-200
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• 2005

In this paper, we proposed the electric circuit using one common arm of H-Bridge Inverters to reduce the number of switching component in multi-level inverter combined with H-Bridge Inverters and Transformers. and furthermore we suggested the new multi-level PWM inverter using PWM level to reduce THD(Total Harmonic Distortion). and we used the switching method that can be same rate of usage at each transformer. Also, we tested the proposed prototype 9-level inverter to clarify the proposed electric circuit and reasonableness of control signal for the proposed multi-level PWM inverter.