• Journal of the Institute of Electronics Engineers of Korea TC
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• v.46 no.2
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• pp.141-146
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• 2009

In this paper, a novel harmonic control circuit has been proposed for the design of high-efficiency power amplifier with Si LDMOSFET. The proposed harmonic control circuit haying the short impedances for the second- and third-harmonic components has been used to design the in/output matching network. The efficiency enhancement effect of the proposed harmonic control circuit is superior to the class-F or inverse class-F harmonic control circuit. Also, when the proposed harmonic control circuit has been adapted to the input matching network as well as the output matching network, the of ficiency enhancement effect of the proposed power amplifier has increased all the more. The measured maximum power added efficiency (PAE) of the proposed power amplifier is 82.68% at 1.71GHz band. Compared with class-F and inverse class-F amplifiers, the measured maximum PAE of the proposed power amplifier has increased in $5.08{\sim}9.91%$.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.47 no.1
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• pp.84-90
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• 2010

In this paper, a novel voltage-controlled oscillator (VCO) using the harmonic control circuit based on the composite right/left-handed (CRLH) transmission lines (TLs) is presented to reduce the phase noise without the reduction of the frequency tuning range and miniaturize the circuit size. The phase noise is reduced by the novel harmonic control circuit having the short impedances for the second- and third-harmonic components. The proposed harmonic control circuit is designed by using the CRLH TLs with the dual-band characteristic by the frequency offset and phase slope of the CRLH TLs. The high-Q resonator has been used to reduce the phase noise, but has the problem of the frequency tuning range reduction. However, the frequency tuning range of the proposed VCO has not been reduced because the phase noise has been reduced without the high-Q resonator. The miniaturization of the circuit size is achieved by using the CRLH TLs instead of the conventional right-handed (RH) TLs. The phase noise of VCO is -119.17 ~ -117.50 dBc/Hz at 100 kHz in the tuning range of 5.731 ~ 5.938 GHz.

• Proceedings of the KIPE Conference
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• 2004.07b
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• pp.587-591
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• 2004

This paper proposes a novel current compensation technique that can eliminate the harmonic currents included in line currents without computation of harmonic current components. A current controller with fast dynamics for an active filter is described. Harmonic currents are directly controlled without the need for sensing and computing the harmonic current of the load current, thus simplifying the control system. Current compensation is done in the time domain, allowing a fast time response. The DC voltage control loop keeps the voltage across the DC capacitor constant. High power factor control by an active filter is described. All control functions are implemented in software using a single-chip microcontroller, thus simplifying the control circuit. Any current-controlled synchronous rectifier can be used as a shunt active filter through only the simple modification of the software and the addition of current sensors. It is shown through experimental results that the proposed controller gives good performance for the shunt active filter.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.45 no.2
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• pp.137-144
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• 2008

In this paper, a novel voltage-controlled oscillator(VCO) using the output matching network based on the harmonic control circuit is presented for improving the phase noise property. The phase noise suppression is achieved through the harmonic control circuit having the short impedances for both second-harmonic and third-harmonic components, which has been connected at the output matching network. Also, we have used the microstrip square open loop multiple split-ring resonator(OLMSRR) having the high-Q property to further reduce the phase noise of VCO. Because the output matching network based on the harmonic control circuit has been used for reducing the phase noise property instead of the High-Q resonator, we can obtain the broad tuning range by the low-Q resonator. The phase noise of the proposed VCO using the output matching network based on the harmonic control circuit and the microstrip square OLMSRR has been $-127.5{\sim}126.33$ dBc/Hz @ 100 kHz in the tuning range, $5.744{\sim}5.839$ GHz. Compared with the reference VCO using the output matching network without the harmonic control circuit and the microstrip line resonator, the phase noise property of the proposed VCO has been improved in 26.66 dB.

• Journal of Power Electronics
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• v.16 no.5
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• pp.1661-1668
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• 2016

A fixed off-time controlled high power factor ac-dc LED driver is proposed in this paper, which employs a novel zero-crossing-compensation (ZCC) circuit based on a fixed off-time controlled scheme. Due to the parasitic parameters of the system, the practical waveforms have a dead region. By detecting the zero-crossing boundary, the proposed ZCC circuit compensates the control signal VCOMP within the dead region, and is invalid above this region. With further optimization of the parameters KR and Kτ of the ZCC circuit, the dead zone can be eliminated and lower THD is achieved. Finally, the chip is implemented in HHNEC 0.5μm 5V/40V HVCMOS process, and a prototype circuit, delivering 7~12W of power to several 3-W LED loads, is tested under AC input voltage ranging from 85V to 265V. The test results indicate that the average total harmonic distortion (THD) of the entire system is approximately 10%, with a minimum of 5.5%, and that the power factor is above 0.955, with a maximum of 0.999.

• Journal of Power Electronics
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• v.12 no.5
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• pp.800-812
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• 2012

This paper analyses the mathematical model and control strategies of a Hybrid Active Power Filter with Injection Circuit (IHAPF). The control strategy based on the load harmonic current detection is selected. A novel control method for a IHAPF, which is based on the analyzed control mathematical model, is proposed. It consists of two closed-control loops. The upper closed-control loop consists of a single fuzzy logic controller and the IHAPF model, while the lower closed-control loop is composed of an Adaptive Network based Fuzzy Inference System (ANFIS) controller, a Neural Generalized Predictive (NGP) regulator and the IHAPF model. The purpose of the lower closed-control loop is to improve the performance of the upper closed-control loop. When compared to other control methods, the simulation and experimental results show that the proposed control method has the advantages of a shorter response time, good online control and very effective harmonics reduction.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2002.07b
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• pp.1093-1096
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• 2002

In this paper, a novel multi voltage inverter system is proposed for reductions of harmonics, which can compensate reactive power. At first, we remove capacitor at input side for reactive power compensation. Secondly, by adding DC voltage to the filter capacitor, it can control power factors as lead-phase according to alterations of loads at power reception. Thirdly, if winding and single phase-bridge inverter(auxiliary circuit) is installed to DC power for reduction of harmonic, waveform of output voltages become to 36-steps. Thus, SVC(static var compensator) systems which can reduce harmonics are designed.

• Journal of Power Electronics
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• v.14 no.1
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• pp.48-60
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• 2014

Multilevel inverters have been widely used for high-voltage and high-power applications. Their performance is greatly superior to that of conventional two-level inverters due to their reduced total harmonic distortion (THD), lower switch ratings, lower electromagnetic interference, and higher dc link voltages. However, they have some disadvantages such as an increased number of components, a complex pulse width modulation control method, and a voltage-balancing problem. In this paper, a novel nine-level reduced switch cascaded multilevel inverter based on a multilevel DC link (MLDCL) inverter topology with reduced switching components is proposed to improve the multilevel inverter performance by compensating the above mentioned disadvantages. This topology requires fewer components when compared to diode clamped, flying capacitor and cascaded inverters and it requires fewer carrier signals and gate drives. Therefore, the overall cost and circuit complexity are greatly reduced. This paper presents modulation methods by a novel reference and multicarrier based PWM schemes for reduced switch cascaded multilevel inverters (RSCMLI). It also compares the performance of the proposed scheme with that of conventional cascaded multilevel inverters (CCMLI). Simulation results from MATLAB/SIMULINK are presented to verify the performance of the nine-level RSCMLI. Finally, a prototype of the nine-level RSCMLI topology is built and tested to show the performance of the inverter through experimental results.

• Journal of Power Electronics
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• v.11 no.4
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• pp.490-498
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• 2011

This paper presents a novel analysis, design, and implementation of a battery charging three-phase high frequency semi-controlled power converter feasible for plug-in hybrid electric vehicles. The main advantages of the proposed topology include high efficiency; due to lower power losses and reduced number of switching elements, high output power density realization, and reduced passive component ratings proportionally to the frequency. Additional advantages also include grid economic utilization by insuring unity power factor operation under different possible conditions and robustness since short-circuit through a leg is not possible. A high but acceptable total harmonic distortion of the generator currents is introduced in the proposed topology which can be viewed as a minor disadvantage when compared to traditional boost rectifiers. A hysteresis control algorithm is proposed to achieve lower current harmonic distortion for the rectifier operation. The rectifier topology concept, the principle of operation, and control scheme are presented. Additionally, a dc-dc converter is also employed in the rectifier-battery connection. Test results on 50-kHz power converter system are presented and discussed to confirm the effectiveness of the proposed topology for PHEV applications.

• The Transactions of the Korean Institute of Electrical Engineers B
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• v.54 no.4
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• pp.195-200
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• 2005

In this paper, we proposed the electric circuit using one common arm of H-Bridge Inverters to reduce the number of switching component in multi-level inverter combined with H-Bridge Inverters and Transformers. and furthermore we suggested the new multi-level PWM inverter using PWM level to reduce THD(Total Harmonic Distortion). and we used the switching method that can be same rate of usage at each transformer. Also, we tested the proposed prototype 9-level inverter to clarify the proposed electric circuit and reasonableness of control signal for the proposed multi-level PWM inverter.