• IEMEK Journal of Embedded Systems and Applications
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• v.13 no.5
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• pp.245-252
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• 2018

Non-volatile RAM devices have been increasingly viewed as an alternative of DRAM main memory system. However some technologies including phase-change memory (PCM) are still suffering from relatively poor write performance as well as limited endurance. In this paper, we introduce a proactive last-level cache management to efficiently hide a low write performance of non-volatile main memory systems. The proposed method significantly reduces the cache miss penalty by proactively evicting the part of cachelines when the non-volatile main memory system is in idle state. Our trace-driven simulation demonstrates 24% performance enhancement, compared with a conventional LRU cache management, on the average.

• Proceedings of the Korean Society of Computer Information Conference
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• 2013.01a
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• pp.195-196
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• 2013

본 논문에서는 NVRAM(Non-volatile Random Access Memory) 주 기억장치를 위한 메모리 컨트롤러를 설계한다. NVRAM의 비 휘발성과 낮은 정적 에너지 소모의 장점을 활용하는 한편, 상대적으로 느린 읽기/쓰기 속도 및 큰 쓰기 전력 소모를 개선하기 위해 새로운 캐시 구조를 제안한다. FPGA를 활용하여 Block RAM 128KB 1차 캐시, 16KB 2차 캐시 및 캐시 컨트롤러를 포함하는 메모리 컨트롤러를 구현하였고 NVRAM은 FeRAM를 사용하였다.

• IEIE Transactions on Smart Processing and Computing
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• v.2 no.4
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• pp.226-239
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• 2013

A number of systems have several on-chip memories with cache memory being one of them. Conventional cache memory consists of SRAM but the ratio of static energy to the total energy of the memory architecture becomes larger as the leakage power of traditional SRAM increases. Spin-Torque Transfer RAM (STT-RAM), which is a variety of Non-Volatile Memory (NVM), has many advantages over SRAM, such as high density, low leakage power, and non-volatility, but it consumes too much writing energy. This study evaluated a wide range of energy consumptions of a two-level cache using NVM partially on a mobile processor. Through a number of experimental evaluations, it was confirmed that the use of NVM partially in the two-level cache effectively reduces energy consumption significantly.

• IEMEK Journal of Embedded Systems and Applications
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• v.13 no.3
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• pp.125-131
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• 2018

STT-RAM is attracting as a next generation Non-volatile memory for replacing cache memory with low leakage energy, high integration and memory access performance similar to SRAM. However, there is problem of write operations as the other Non_volatile memory. Hybrid cache memory using SRAM and STT-RAM is attracting attention as a cache memory structure with lowe power consumption. Despite this, reducing the leakage energy consumption by the STT-RAM is still lacking access to the Dynamic energy. In this paper, we proposed as energy management method such as a way-selection approach for hybrid L2 cache fo SRAM and STT-RAM and memory selection method of write/read operation. According to the simulation results, the proposed hybrid cache memory reduced the average energy consumption by 40% on SPEC CPU 2006, compared with SRAM cache memory.

• JSTS:Journal of Semiconductor Technology and Science
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• v.5 no.4
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• pp.262-269
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• 2005

Semiconductor scientists and engineers ideally desire the faster but the cheaper non-volatile memory devices. In practice, no single device satisfies this desire because a faster device is expensive and a cheaper is slow. Therefore, in this paper, we use heterogeneous non-volatile memories and construct an efficient hierarchy for them. First, a small RAM device (e.g., MRAM, FRAM, and PRAM) is used as a write buffer of flash memory devices. Since the buffer is faster and does not have an erase operation, write can be done quickly in the buffer, making the write latency short. Also, if a write is requested to a data stored in the buffer, the write is directly processed in the buffer, reducing one write operation to flash storages. Second, we use many types of flash memories (e.g., SLC and MLC flash memories) in order to reduce the overall storage cost. Specifically, write requests are classified into two types, hot and cold, where hot data is vulnerable to be modified in the near future. Only hot data is stored in the faster SLC flash, while the cold is kept in slower MLC flash or NOR flash. The evaluation results show that the proposed hierarchy is effective at improving the access time of flash memory storages in a cost-effective manner thanks to the locality in memory accesses.

• Proceedings of the Korean Information Science Society Conference
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• 2005.07a
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• pp.844-846
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• 2005

차세대 비휘발성 메모리(Non-Volatile RAM, 이후 NVRAM)의 사용이 현실화 되면서 이를 활용한 저장 장치의 성능 개선 연구가 활발히 진행되고 있다. 본 논문에서는 NVRAM을 이용한 플래시 파일 시스템의 성능 향상 방법을 제안한다. 우선 자주 갱신 되는 정보를 NVRAM에 유지시켜 플래시 메모리의 덮어쓰기(overwrite)로 인한 성능 저하 문제를 개선한다. 또한 NVRAM에 파일시스템의 메타 정보 위치를 유지하여 파일 시스템을 마운트할 때 요구되는 플래시 메모리의 탐색 공간을 줄인다. 실험 결과 마운팅 시간이 줄고 플래시 메모리의 접근 횟수가 감소함을 확인하였다.

• Journal of KIISE:Computing Practices and Letters
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• v.14 no.5
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• pp.537-541
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• 2008

Log-Structured File System(LFS) is a disk based file system that is optimized for improving the write performance. LFS gathers dirty data in memory as long as possible, and flushes all dirty data sequentially at once. In a real system, however, maintaining dirty data in memory should be flushed into a disk to meet file system consistency issues even if more memory is still available. This synchronizations increase the cleaner overhead of LFS and make LFS to write down more metadata into a disk. In this paper, by adapting Non-volatile RAM(NV-RAM) we modifies LFS and virtual memory subsystem to guarantee that LFS could gather enough dirty data in the memory and reduce small disk writes. By doing so, we improves the performance of LFS by around 2.5 times than the original LFS.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.65 no.8
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• pp.1369-1375
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• 2016

A rapid progress of the next-generation non-volatile memory device has been made in recent years. Metal/insulator/Metal multi-layer structure resistive RAM(ReRAM) has attracted a great deal of attention because it has advantages of simple fabrication, low cost, low power consumption, and low operating voltage. This paper describes the working principle of the ReRAM device, a review of fabrication techniques, and characteristics of flexible ReRAM devices using graphene oxide as an insulating layer and ReRAM devices using multi-layered insulator. The switching characteristics of the above ReRAM devices have been compared. The oxidized graphene could be employed as an insulator of next generation ReRAM devices.

• Proceedings of the Korean Information Science Society Conference
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• 2007.06a
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• pp.256-257
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• 2007

• Journal of KIISE:Computer Systems and Theory
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• v.35 no.2
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• pp.94-101
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• 2008

Non-volatile RAM (NVRAM) is a form of next-generation memory that has both characteristics of nonvolatility and byte addressability each of which can be found in nonvolatile storage and RAM, respectively. The advent of NVRAM may possibly bring about drastic changes to the system software landscape. When NVRAM is efficiently exploited in the system software layer, we expect that the system performance can be significantly improved. In this regards, we attempt to develop a new Flash file system, named MiNVFS (Metadata in NVram File System). MiNVFS maintains all the metadata in NVRAM, while storing all file data in Flash memory. In this paper, we present quantitative experimental results that show how much performance gains can be possible by exploiting NVRAM. Compared to YAFFS, a typical Flash file system, we show that MiNVFS requires only minimal time for mounting. MiNVFS outperforms YAFFS by an average of around 400% in terms of the total execution time for the realistic workloads that we considered.