• 대한전기학회:학술대회논문집
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• 대한전기학회 1998년도 하계학술대회 논문집 G
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• pp.2296-2298
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• 1998

In this paper, an on-chip learning pulse-mode digital neural network with a massively parallel yet compact and flexible network architecture is suggested. Algebraic neural operations are replaced by stochastic processes using pseudo-random sequences and simple logic gates are used as basic computing elements. Using Back-propagation algorithm both feed-forward and learning phases are efficiently implemented with simple logical gates. RNG architecture using LFSR and barrel shifter are adopted to avoid some correlation between pulse trains. Suggested network is designed in digital circuit and its performance is verified by computer simulation.

• ETRI Journal
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• 제31권2호
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• pp.111-120
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• 2009

Network-on-chip (NoC) architecture provides a highper-formance communication infrastructure for system-on-chip designs. Circuit-switched networks guarantee transmission latency and throughput; hence, they are suitable for NoC architecture with real-time traffic. In this paper, we propose an efficient integrated scheme which automatically maps application tasks onto NoC tiles, establishes communication circuits, and allocates a proper bandwidth for each circuit. Simulation results show that the average waiting times of packets in a switch in $6{\times}6$6, $8{\times}8$, and $10{\times}10$ mesh NoC networks are 0.59, 0.62, and 0.61, respectively. The latency of circuits is significantly decreased. Furthermore, the buffer of a switch in NoC only needs to accommodate the data of one time slot. The cost of the switch in the circuit-switched network can be reduced using our scheme. Our design provides an effective solution for a critical step in NoC design.

• 전자공학회논문지
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• 제50권1호
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• pp.166-173
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• 2013

SoC내의 IP 개수 및 데이터 통신량이 증가함에 따라 온칩 크로스바 네트워크가 SoC의 중추 연결망으로서 널리 사용되어지고 있다. 온칩 크로스바 네트워크는 여러 개의 크로스바 스위치들과 이들간의 연결로 이루어지는데, 시스템의 복잡도가 증가함에 따라 IP들과 스위치들간의 연결 형태를 결정하는 것, 즉 토폴로지를 결정하는 것이 점점 복잡해지고 있다. 이 문제를 해결하기 위해 본 논문에서는 목표 시스템의 칩내 통신 특성을 고려하여 최적의 온칩 크로스바 네트워크의 토폴로지를 찾아주는 방법을 제안한다. 제안하는 토폴로지 합성 방법은 mixed integer linear programming(MIILP)를 이용하여 다른 휴리스틱 합성 방법과 달리 전역 최적점(global optimum)을 찾을 수 있는 장점이 있다. 또한, 기존에 제안 되었던 MILP를 이용한 토폴로지 합성 방법들이 토폴로지를 표현하는데 IP 노드들과 스위치들 간의 인접 행렬들을 이용했던 것과 달리, 본 논문에서는 IP들 간통신을 표현하는 엣지들을 기본으로 하는 새로운 표현 방식을 제안한다. 실험 결과 본 논문에서 제안하는 새로운 MILP 표현 방식을 이용할 경우 기존 MILP 표현 방식을 이용했을 때보다 4개의 예제들에 대해 합성 속도가 평균 77.1 배 향상되었다.

• Journal of Mechanical Science and Technology
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• 제14권6호
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• pp.622-632
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• 2000

In a high precision vertical machining center, the estimation of cutting forces is important for many reasons such as prediction of chatter vibration, surface roughness and so on. The cutting forces are difficult to predict because they are very complex and time variant. In order to predict the cutting forces of end-milling processes for various cutting conditions, their mathematical model is important and the model is based on chip load, cutting geometry, and the relationship between cutting forces and chip loads. Specific cutting force coefficients of the model have been obtained as interpolation function types by averaging forces of cutting tests. In this paper the coefficients are obtained by neural network and the results of the conventional method and those of the proposed method are compared. The results show that the neural network method gives more correct values than the function type and that in the learning stage as the omitted number of experimental data increase the average errors increase as well.

• 한국화재소방학회논문지
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• 제10권2호
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• pp.28-39
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• 1996

A recently developed electro-thermal simulation methodology is used to analyze the behavior of a PWM(Pulse-Width-Modulated) voltage source inverter which uses IGBT(Insulated Gate Bipolar Transistor) as the switching devices. In the electro-thermal network simulation methdology, the simulator solves for the temperature distribution within the power semiconductor devices(IGBT electro-thermal model), control logic circuitry, the IGBT gate drivers, the thermal network component models for the power silicon chips, package, and heat sinks as well as the current and voltage within the electrical network. The thermal network describes the flow of heat form the chip surface through the package and heat sink and thus determines the evolution of the chip surface temperature used by the power semiconductor device models. The thermal component model for the device silicon chip, packages, and heat sink are developed by discretizing the nonlinear heat diffusion equation and are represented in component from so that the thermal component models for various package and heat sink can be readily connected to on another to form the thermal network.

• 한국음향학회:학술대회논문집
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• 한국음향학회 1993년도 학술논문발표회 논문집 제12권 1호
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• pp.117-120
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• 1993

In this paper, we explore the possibility of URAN(Universally Reconstructable Artificial Neural-network) VLSI chip for speech recognition. URAN, a newly developed analog-digital hybrid neural chip, is discussed in respects to its input, output, and weight accuracy and their relations to its performance on speaker independent digit recognition. Multi-layer perceptron(MLP) nets including a large frame input layer are used to recognize a digit syllable at a forward retrieval. The simulation results using the full and limited floating precision computations for the input, output, and weight variables of the network give the comparable classification performance. An MLP with piecewise linear hidden and output units is also trained successfully using low accuracy computation.

• 한국지능시스템학회논문지
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• 제10권3호
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• pp.270-279
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• 2000

본 논문은 확률 펄스연산을 이용한 신경회로망이 on-Chip학습 알고리즘에 대해 기술하였다. 확률 펄스 연산은 임이의 펄스열에서 1과 0이 발생할 확률을 통해 표현된 수를 사용하여 계산하는 것을 일컫는다. 이러한 확률연산을 신경회로망에 적용하면 하드웨어 구현먼적을 줄일 수 있다는 것과 확률적인 특징으로 인해 지역 최소값으로부터 빠져 나와 광역 최적해에 도달할 수 있다는 장점을 갖고 있다. 또한 본 연구에서는 칩 냅에 학습할 수 있는 on-chip학습 알고리즘을 역전파 학습 알고리즘으로부터 유도하였다. 이렇게 유도된 알고리즘을 검증하기 위하여 비선형 패턴분리문제를 모의실험 하였다. 도한 활자체 및 필기체 숫자 인식에도 적용하여 좋은 결과를 얻었다.

• 마이크로전자및패키징학회지
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• 제24권3호
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• pp.1-6
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• 2017

As the performance and density of IC devices increase, especially the clock frequency increases, power grid network integrity problems become more challenging. To resolve these power integrity problems, the use of passive devices such as resistor, inductor, and capacitor is very important. To manage the power integrity with little noise or ripple, decoupling capacitors are essential in electronic packaging. The decoupling capacitors are classified into voltage regulator capacitor, board capacitor, package capacitor, and on-chip capacitor. For next generation packaging technologies such as 3D packaging or wafer level packaging on-chip MIM decoupling capacitor is the key element for power distribution and delivery management. This paper reviews the use and necessity of on-chip decoupling capacitor.

• JSTS:Journal of Semiconductor Technology and Science
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• 제15권1호
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• pp.85-95
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• 2015

Network-on-chip (NoC) has evolved to overcome the issues of traditional bus-based on-chip interconnect. In NoC-reuse as TAM, the test schedulers are constrained with the topological position of cores and test access points, which may negatively affect the test time. This paper presents a scalable hybrid test data transportation scheme that allows to simultaneously test multiple heterogeneous cores of NoC-based SoCs, while reusing NoC as TAM. In the proposed test scheme, single test stimuli set of multiple CUTs is embedded into each flit of the test stimuli packets and those packets are multicast to the targeted CUTs. However, the test response packets of each CUT are unicast towards the tester. To reduce network load, a flit is filled with maximum possible test response sets before unicasting towards the tester. With the aid of Verilog and analytical simulations, the proposed scheme is proved effective and the results are compared with some recent techniques.

• International Journal of Control, Automation, and Systems
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• 제4권5호
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• pp.567-574
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• 2006

This paper presents the hardware implementation of a neural network controller for a nonlinear system with a micro-controller unit (MCU) and a field programmable gate array (FPGA) chip. As an on-line learning algorithm of a neural network, the reference compensation technique has been implemented on an MCU, while PID controllers with other functions such as counters and PWM generators are implemented on an FPGA chip. Interface between an MCU and a field programmable gate array (FPGA) chip has been developed to complete hardware implementation of a neural controller. The developed neural control hardware has been tested for balancing the inverted pendulum while controlling a desired trajectory of a cart as a nonlinear system.