• Journal of the Korean Institute of Telematics and Electronics B
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• v.30B no.10
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• pp.69-76
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• 1993

In this paper we propose a design of a digital neuron processor using the residue number system for efficient matrix.vector multiplication involved in neural processing. Since the residue number system needs no carry propagation for modulus operations, the neuron processor can perform multiplication considerably fast. We also propose a high speed algorithm for computing the sigmoid function using the specially designed look-up table. Our method can be implemented area-effectively using the current technology of digital VLSI and siumlation results positively demonstrate the feasibility of our method. The proposed method would expected to adopt for application field of digital neural network, because it could be realized to currently developed digital VLSI Technology.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.32 no.1B
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• pp.17-21
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• 2007

In this paper, we propose new on-line processor management algorithms that manage heterogeneous multimedia services while maximizing energy efficiency. These online management mechanisms are combined in an integrated scheme for higher system performance and energy efficiency. The most important feature of our proposed scheme is its adaptability, flexibility and responsiveness to current network conditions. Simulation results clearly indicate the superior performance of our proposed scheme to strike the appropriate performance balance between contradictory requirements.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.34C no.5
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• pp.19-32
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• 1997

So far, the multiple path MINs to provide redundant paths in the traditional UPP MINs have been realized by adding additional hardware such as extra stages, duplicated data links, or multiple copies of sthe MIN. And the traditional MINs do not exploit locality: communication with all processor-memory paris takes the same amount of time. Also so far there has been little progress for exploiting locality of reference in MINs. In this paper, we present a new topology MIN, hybrid MIN that is constructed with 2N-3 SEs which is far fewer SEs than that of traditional MINs. Although the hybrid MIN is constructed with 2N-3 SEs, the hybrid MIN satisfies full access capability (FAC) and has redundant paths(but providing single path for 2 memory modules of each processor). Moreover the has redundant paths (but providing single path for 2 memory modules of each processor). Moreover the Hybrid MIN provides shortcut path between pairs which have frequent dat acommunication (locality of reference). Its performance under varing degrees of localized communication is analyzed.

• Journal of the Korean Institute of Intelligent Systems
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• v.11 no.8
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• pp.746-753
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• 2001

In this paper, we review the basic concept of Evolvable Hardware first. And we examine genetic algorithm processor and hardware reconfiguration method and implementation. By considering complexity and performance of hardware at the same time, we design genetic algorithm processor using modularization and parallel processing method. And we design frame that has connection structure and logic block on FPGA, and embody reconfigurable hardware that do so that this frame may be reconstructed by RAM. Also we implemented ECANS that information processing system such as living creatures'brain using this hardware reconfiguration method. And we apply ECANS which is implemented using the concept of Evolvable Hardware to time-series prediction problem in order to verify the effectiveness.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.13 no.1
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• pp.28-40
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• 1988

Nowadays, the needs for intelligence of communication equipments and the cost down of micro processor are showing a tendency to have multi0processor in a single system. In this paper, based on the Reserved Bus Topology which is propoed in "A study on he Communication Method between the adjacent processor", the software and hardware is designed and developed. And tha validity of this method and the utility of designed software and hardware functions are also verified through exepriments.epriments.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.8 no.4
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• pp.833-837
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• 2004

The iris image recognition system realization using DSP processor for the faster real-time processing is presented in this paper. The system is composed of CCD camera, DSP processing and network part to link the communication. The system based on high speed DSP processor leads the iris recognition processing time to be faster. The simulation results in 0.9sec below approximately.

• Proceedings of the Korean Information Science Society Conference
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• 2003.04d
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• pp.503-505
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• 2003

패킷망을 통해 음성, 영상, 데이터를 동시에 제공할 수 있는 차세대 네트워크(NGN) 개념이 제안되어 현재 네트워크 상에 전개되어 가고 있다. 하지만 NGN의 Softswitch의 구성을 위해서는 현재의 PSTN 내의 Class 4/5 switch를 NGN의 구성에 맞게 끔 Access Gateway 및 Media Gateway로 교체해 나가야 하며 교체 후에도 소비자의 새로운 서비스 신설 요구에 신속하게 부합하기 위하여 기존 시스템의 서비스 중단없이 새로운 서비스 및 신규 프로토콜을 신속히 전개할 수 있는 개념은 필수적인 요소가 되었다. 이러한 점을 지원하기 위하여 본 논문에서는 개방형 네트워크 아키텍처 접근 방식인 Active Network의 개념을 응용한 차세대네트워크 Media Gateway Controller내의 이산 메커니즘 적용 Active Packet Processor도입하였다.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2020.11a
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• pp.106-107
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• 2020

본 논문에서는 촬영과 동시에 유통되는 생방송 영상의 실시간 지적재산권 보호를 위한 Convolutional Neural Network를 기반으로 하는 워터마킹 프로세서의 구조를 제안한다. 제안하는 워터마킹 프로세서는 전처리 네트워크와 삽입 네트워크를 최적화하여 ASIC 칩으로 제작한다. 이는 영상을 입력으로 하는 딥 러닝 분야에서 많이 사용되는 CNN을 기반으로 하기 때문에 일반적인 딥 러닝 가속기 설계로 간주된다.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.5C
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• pp.454-464
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• 2002

In the ATM-PON (Asynchronous Transfer Mode-Passive Optical Network), the downstream cell transmitted by an OLT is broadcast to all ONUs. The ONU receives selectively its own cells by VP filtering. On the other hand, the upstream cell can be transmitted by ONU in the case of receiving a grant from the OLT. After providing the grant to an ONU, the OLT expects the arrival of a cell after an elapse of the equalized round trip delay. ITU-T G.983.1 recommends that one bit error is allowed between the expected arrival time and the actual arrival time at the OLT. Because the ONU processes the different delay to each type of grant (ranging, user cell, and mimi-slot grant), it is not simple to design the transmission part of ONU. In this paper, we implement a grant processor which provides the delay accurately in the ONU TC chip with the FPGA. For the given equalized delay, it deals with the delay for the cell, the byte, and the bit unit by using the shift register, the byte counter, and the D flip-flop, respectively. We verify the operation of the grant processor by the time simulation and the measurement of the optical board output.

• Journal of the Institute of Convergence Signal Processing
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• v.11 no.1
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• pp.53-62
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• 2010

Recently, various industrial embedded systems including vehicles controlled electronically are evolving to distributed multi-micro controller system. Accordingly, there is a need for standard CAN(Controller Area Network) protocol that ensures high stability and reliability of communication and is simple to construct object-oriented system with high control efficiency. CAN communication interface used general-purpose processor doesn't have many limitations in various application development because of fixed hardware architecture. This paper design and implement a CAN communication interface system based on FPGA. It is verified function and performance of system through monitoring communication with existing AT90CAN128 controller. Implemented CAN communication interface can be reused in development of application systems based on FPGA. And it provides low-cost, small-size and low-power design advantages.