• The Journal of Korean Institute of Communications and Information Sciences
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• v.18 no.7
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• pp.1018-1027
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• 1993

In this thesis, we evaluate the performance of the TDX-IB/ISDN Switching System ISS (ISDN Subscriber Subsystem) which is the ISDN user-network interface module. For this evaluation, performance indices are established and major performance parameters which influence message processing are extracted by studying the ISS structure and mechanism. To reflect these parameters, simulation model is developed and simulated. From the result of maximum throughput, message delay time, etc. , ISS message processing capability is evaluated and several method to enhance the system performance is proposed, by analyzing the system bottleneck element.

• Journal of the Microelectronics and Packaging Society
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• v.20 no.4
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• pp.69-74
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• 2013

In this paper, the impact of integrating large number of I/O (Input-Output) and Core power Delivery Network (PDN) on a 6 layers Flip-Chip Ball Grid Array (FCBGA) package is investigated. The impact of core induced supply noise on high-speed I/O interfaces, and high-speed I/O interface's supply noise coupling to adjacent high-speed I/O interfaces' jitter impact are studied. Concurrent stress validation software is used to induce SSO noise on each individual I/O interfaces; and at the same time; periodic noise is introduced from Core PDN into the I/O PDN domain. In order to have the maximum coupling impact, a prototype package is designed to merge the I/O and Core PDN as one while impact on jitter on each I/O interfaces are investigated. In order to understand the impact of the Core to I/O and I/O to I/O noise, the on-die noise measurements were measured and results were compared with the original PDN where each I/O and Core PDN are standalone and isolated are used as a benchmark.

• Convergence Security Journal
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• v.13 no.6
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• pp.3-9
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• 2013

With the rapidly changing information communication environment and development of technologies, the informati on networks are evolved from traditional fixed form to an active variable network that flexible large variety of data can be transferred. To reflect the needs of users, the next generation using DWDM (Dense Wavelength Division M ultiplexing) transmission system and OXC (Optical Cross Connect) form a dynamic network. After that GMPLS (Ge neralized Multi-Protocol Label Switching) can be introduced to dynamically manage and control the Reconfigurable Optical Add-drop Multiplexer (ROADM)/Photonic Cross Connect (PXC) based network. This paper propose a softw are architecture of Path Computation Element (PCE) protocol that has proposed by Internet Engineering Task Force (IETF) to path computation. The functional blocks and Application Programming Interface (API) of the PCE protoco l implementation are also presented.

• Journal of KIISE:Computer Systems and Theory
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• v.31 no.11
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• pp.626-634
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• 2004

In a client-server model, network server systems suffer from both heavy communication and computational loads. While communication channels become increasingly speedy, the existing protocol stack architectures still include mainly three performance bottlenecks of protocol stack processing, system call, and network interrupt overheads. To address these obstacles, in this paper we present a host-independent network system where a network interface card (NIC) is utilized in an efficient manner. First, by offloading network-related portion to the NIC, the host can fully utilize its processing power for other useful purposes. Second, it eliminates the system call overhead, such as context-switching and memory copy operations, since the host communicates with the NIC through its user-level libraries. Third, it a] so reduces the network interrupt operation count as the host handles the interrupt in a segment instead of a packet. The experimental results show that the proposed network system reduces the host CPU overhead for communication system by 68-71%. It also shows that the proposed system improves the communication speed by 11-83% under heavy computational and communication load conditions.

• Proceedings of the IEEK Conference
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• 1999.11a
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• pp.113-116
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• 1999

This paper presents a hardware architecture of AAL(ATM Adaptation Layer) type 2 switch. The proposed architecture can assign and configure maximum AAL2 CID limit. AAL2 is the protocol which has been recommended by ITU-T and ATM-Forum for low bit rate delay sensitive services. The architecture assumes 155 Mbps STM-1/STS-3c physical interface, maximum VCC can be 64K connections. It can support maximum 16,384M AAL2 connections. For efficient use of peripheral memory, a concept of segment address was proposed. The proposed AAL2 switch hardware architecture can be used in ATM network as a standalone server or embedded module in a ATM switching system.

• Information and Communications Magazine
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• v.6 no.1
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• pp.33-43
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• 1989

The subscriber & signal processing subystem of digital switching system TDX-1B has increased double in its capacity than TDX-1A, containing maximum 1024 subscribers per rack. It consists of subscriber interface devices, concentrating devices, signalling devices and controlling device in order to connect subscriber lines to switch network and supply subscriber signals for subscribers. This paper describes development procedures, principal functions of TDX-1B subscriber $ signal processing devices and the results.

• ETRI Journal
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• v.44 no.4
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• pp.695-707
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• 2022

As for the insufficient nature of the fossil fuel resources, the renewable energies as alternative fuels are imperative and highly heeded. To deliver the required electric power to the industrial and domestic consumers from DC renewable energy sources like fuel cell (FC), the power converter operates as an adjustable interface device. This paper suggests a new boost structure to provide the required voltage with wide range gain for FC power source. The proposed structure based on the boost converter and the quazi network, the so-called SBQN, can effectively enhance the FC functionality against its high operational sensitivity to experience low current ripple and also propagate voltage and current with low stress across its semiconductors. Furthermore, the switching power losses have been decreased to make this structure more durable. A full operational analysis of the proposed SBQN and its advantages over the conventional and famous structures has been compared and explained. Furthermore, a prototype of the single-phase converter has been constructed and tested in the laboratory.

• International Journal of Internet, Broadcasting and Communication
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• v.14 no.1
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• pp.1-9
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• 2022

Recently, a large number of cryptocurrencies and block chains have been continuously released. However, these cryptocurrencies and block chains are open to users without authorized verification and testing procedures, causing various reliability problems. Existing cryptocurrencies and blockchain test methods build a blockchain Testnet for a certain period of time by the developer without external verification by a third party, and after repeatedly self-testing and self-operating processes, commercialization is in progress by switching to the Mainnet. This self-verification method does not guarantee objectivity and publicness, and high reliability of customers cannot be realized. This study proposes a cryptocurrency and blockchain test interface and test control system as a third-party open test method.

• Journal of KIISE:Computing Practices and Letters
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• v.6 no.4
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• pp.421-429
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• 2000

In present, ATM integrated switching system has been developed to a mixed modules that complexed switching system including maintenance, operation based on B-ISDN/LAN service and plug-in module, , which runs on workstation computer system. Meanwhile, workstation has HMI operation system feature including file system management, time management, graphic processing, TMN agent function. The workstation has communicated with between ATM switching module and clients. This computer system architecture has much burden messages communication among processes or processor. These messages communication consume system resources which are socket, message queue, IO device files, regular files, and so on. Therefore, in this paper we proposed new performance modeling with this system architecture. We will analyze the system bottleneck and improve system performance. In addition, in the future, the system has many additional features should be migrated to workstation system, we need previously to evaluate system bottleneck and redesign it. In performance model, we use queueing network model and the simulation package is used PDQ and C-program.

• Journal of KIISE:Information Networking
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• v.29 no.4
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• pp.405-411
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• 2002

Open interfaces in the optica] Internet have been progressed by OIF's ISI, ITU-T ASTN's CCI and IETF's GSMP extensions with optical switching. These open interfaces enable the separation between the control plane and the optical transport plane. This separation allows flexibility in the network, but it suffers more setup delay than the traditional switch-by-switch connection setup. We propose the parallel interworking model, which will reduce the connection setup delay in the open interface of optical Internet. Based on the switch controller's caching capability about networks states, the parallel interworking procedures between signaling protocol and GSMP protocol are performed in the switch controller. We simulated and evaluated our proposed parallel interworking model and the existing sequential interworking model in terms of a connection setup delay and a completion ratio. We observed that the completion ratios of the two interworking models were quite close. However the connection setup delay of parallel interworking model is improved by about 30% compared with that of the sequential interworking model.