• Journal of the Institute of Electronics and Information Engineers
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• v.52 no.1
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• pp.61-68
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• 2015

In recent times, the median filtering (MF) detector as a forensic tool for the recovery of forgery images' processing history has concerned broad interest. For the classification of MF image, MF detector should be designed with smaller feature set and higher detection ratio. This paper presents a novel method for the detection of MF in altered images. It is transformed from BMP to several kinds of MF image by the median window size. The difference distribution values are computed according to the window sizes and then the values construct the feature set same as the MF window size. For the MF detector, the feature set transformed to the model specification which is computed using latent growth modeling (LGM). Through experiments, the test image is classified by the discriminant into two classes: the true positive (TP) and the false negative (FN). It confirms that the proposed algorithm is to be outstanding performance when the minimum distance average is 0.119 in the confusion of TP and FN for the effectivity of classification.

• Proceedings of the KIEE Conference
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• 1988.11a
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• pp.249-251
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• 1988

In this paper, the negative ion mobility of $SF_6$ is determined using as a negative ion detector the burst pulse which is triggered in a positive point-plane gap by electrons detached from negative ions near the anode point. The result obtained for the negative ion mobility for zero field at atmospheric pressure is $0.57cm^2v^{-1}s^{-1}$.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.18 no.9
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• pp.2176-2182
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• 2014

In this paper, a phase locked loop with suppressed power supply noise has been proposed. The added negative feedback loop of voltage controlled oscillator(VCO) and power noise detector suppresses the power noise induced jitter variation of VCO down to 1/3. The power noise detector is the modified circuit of frequency voltage converter. The proposed PLL has been designed based on a 1.8V 0.18um CMOS process and proved by HSPICE simulation.

• Journal of the Korean Institute of Intelligent Systems
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• v.14 no.4
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• pp.451-456
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• 2004

Signature based intrusion detection system (IDS), having stored rules for detecting intrusions at the library, judges whether new inputs are intrusion or not by matching them with the new inputs. However their policy has two restrictions generally. First, when they couldn't make rules against new intrusions, false negative (FN) errors may are taken place. Second, when they made a lot of rules for maintaining diversification, the amount of resources grows larger proportional to their amount. In this paper, we propose the learning algorithm which can evolve the competent of anomaly detectors having the ability to detect anomalous attacks by genetic algorithm. The anomaly detectors are the population be composed of by following the negative selection procedure of the biological immune system. To show the effectiveness of proposed system, we apply the learning algorithm to the artificial network environment, which is a computer security system.

• Journal of the Korean Institute of Telematics and Electronics
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• v.10 no.5
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• pp.7-15
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• 1973

The gain stability of the nuclear pulse ampifiers with negative feedback for such a fast pulse input as the step voltge or the nuclear radiation detector pulse is analyzed in detail and the experimental results are given. It is shown that a few risetime should elapse to get the full effect of the negative feedback upon the liearity and the stability of the amplifiers for the fast pulse input, and to reduce this limitation the risetime of the negative feedback amplifier must be designed to be short compared with the width of the input pulse.

• Proceedings of the IEEK Conference
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• 2001.06b
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• pp.243-246
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• 2001

At atmosphere photoluminescence(PL) of porous silicon(PSi) decreases and peak wave number of PL is shifted to blue region. When PS is used light detector, the ageing effects are negative phenomena. For controling ageing effects, this paper uses Polymers.

• The Transactions of the Korean Institute of Power Electronics
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• v.26 no.4
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• pp.271-276
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• 2021

Arc fault detector based on multilevel DWT with analysis of high-frequency noise components over 100 kHz is proposed in this study to improve the performance in detecting serial arcs and distinguishing them from inverter noise in PV systems. PV inverters generally operate at a frequency range of 20-50 kHz for switching operation and maximum power tracking control, and the effect of these frequency components on the signal for arc detection leads to negative arc detection. High-speed ADC and multilevel DWT are used in this study to analyze frequency components above 100 kHz. Such high frequency components are less influenced by inverter noise and utilized to detect as well as separate DC series arc from inverter noise. Arc detectors identify the input current of PV inverters using a Rogowski coil. The sensed signal is filtered, amplified, and used in 800kSPS ADC and DWT analysis and arc occurrence determination in DSP. An arc detection simulation facility in UL1699B was constructed and AFD tests the proposed detector were conducted to verify the performance of arc detection and performance of distinction of the negative arc. The satisfactory performance of the arc detector meets the standard of arc detection and extinguishing time of UL1699B with an arc detection time of approximately 0.11 seconds.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.24 no.11
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• pp.1104-1112
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• 2013

This paper presents a wideband Colpitts voltage controlled oscillator(VCO) with nanosecond startup time and a center frequency of 8.35 GHz for a new bubble-type motion detector that has a bubble-layer detection zone at the specific distance from itself. The VCO circuit consists of two parts; one is a negative resistance part with a HEMT device and Colpitts feedback structure and the other is a resonator part with a varactor diode and shorted shunt microstrip line. The shorted shunt microstrip line and series capacitor are utilized to compensate for the input reactance of the packaged HEMT that changes from capacitive values to inductive values at 8.1 GHz due to parasitic package inductance. By tuning the feedback capacitors which determine negative resistance values, this paper also investigates startup time improvement with the negative resistance variation and tuning bandwidth improvement with the reactance slope variation of the negative resistance part. The VCO measurement shows the tuning bandwidth of 2.3 GHz(28 %), the output power of 4.1~7.5 dBm and the startup time of less than 2 nsec.

• Nuclear Engineering and Technology
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• v.51 no.4
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• pp.1081-1090
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• 2019

Detailed pulse shape analysis of a Geiger-$M{\ddot{u}}ller$ counter is performed to understand the pulse shape dependence on operating voltage. New data is presented to demonstrate that not all pulses generated in a GM counter are identical. In fact, there is a strong correlation between the operating voltage and the pulse shape. Similar to detector deadtime, pulse shapes fall in three distinct regions. For low voltage region, where deadtime was reported to reduce with increasing voltage, pulse generated in this region was observed to have a fixed pulse width with a variable tail. The pulse width and fall time of the tail was observed to be a function of applied voltage; exponentially reducing with increasing voltage with an exponent of negative 6E-04 and 2E-03 respectively. The second region showed a pulse without any significant tail. During this time the detector deadtime was earlier reported to be at its minimum. The highest voltage region demonstrated a different deadtime mechanism where the second pulse was reduced in width. During this time the deadtime seemed to be increasing with increasing voltage. This data allows us to gain some unique insight into the phenomenon of GM detector deadtime not reported thus far.

• Proceedings of the IEEK Conference
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• 1999.11a
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• pp.275-278
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• 1999

In this paper, Dual PFD(Phase Frequency Detector) with improved phase locking time is proposed. The proposed PFD consists of positive and negative edge triggered D flip-flop. In order to confirm the characteristics of proposed PFD, HSPICE simulations are performed using a 0.25${\mu}{\textrm}{m}$ CMOS process. As a result of simulations, the proposed PFD has a characteristic of fast phase locking time with dead zone free.