Proceedings of the IEEK Conference (대한전자공학회:학술대회논문집)

The Institute of Electronics and Information Engineers (대한전자공학회)
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Design of Dual PFD with Improved Phase Locking Time

위상동기시간을 개선한 Dual PFD 설계

  • 이준호 (전북대학교 전자정보공학부) ;
  • 손주호 (전북대학교 전자정보공학부) ;
  • 김선홍 (전북대학교 전자정보공학부) ;
  • 김동용 (전북대학교 전자정보공학부)
  • Published : 1999.11.01
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Abstract

In this paper, Dual PFD(Phase Frequency Detector) with improved phase locking time is proposed. The proposed PFD consists of positive and negative edge triggered D flip-flop. In order to confirm the characteristics of proposed PFD, HSPICE simulations are performed using a 0.25${\mu}{\textrm}{m}$ CMOS process. As a result of simulations, the proposed PFD has a characteristic of fast phase locking time with dead zone free.

Keywords