• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 1999년도 춘계학술대회 논문집
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• pp.485-488
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• 1999

In this paper, the effects of back-gate bias on n-channel SOI MOSFETs has been systematically investigated. Back-gate surface is accumulated when negative bias is applied. It is found that the driving current ability of SOI MOSFETs is reduced because the threshold voltage and subthreshold slope are increased and transconductance is decreased due to the hole accumulation in Si body.

• 한국표면공학회지
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• 제46권1호
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• pp.29-35
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• 2013

The effect of DC bias on the growth of nanocrystalline diamond films on silicon substrate by microwave plasma chemical vapor deposition has been studied varying the substrate temperature (400, 500, 600, and $700^{\circ}C$), deposition time (0.5, 1, and 2h), and bias voltage (-50, -100, -150, and -200 V) at the microwave power of 1.2 kW, working pressure of 110 torr, and gas ratio of Ar/1%$CH_4$. In the case of low negative bias voltages (-50 and -100 V), the diamond particles were observed to grow to thin film slower than the case without bias. Applying the moderate DC bias is believed to induce the bombardment of energetic carbon and argon ions on the substrate to result in etching the surfaces of growing diamond particles or film. In the case of higher negative voltages (-150 and -200 V), the growth rate of diamond film increased with the increasing DC bias. Applying the higher DC bias increased the number of nucleation sites, and, subsequently, enhanced the film growth rate. Under the -150 V bias, the height (h) of diamond films exhibited an $h=k{\sqrt{t}}$ relationship with deposition time (t), where the growth rate constant (k) showed an Arrhenius relationship with the activation energy of 7.19 kcal/mol. The rate determining step is believed to be the surface diffusion of activated carbon species, but the more subtle theoretical treatment is required for the more precise interpretation.

• 한국진공학회지
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• 제2권4호
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• pp.501-506
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• 1993

The spatial potential distribution of electron cyclotron resonance plasma is measured as a function of tehsubstrate DC bias by Langmuir probe method. It is observed that the substrate DC bias changes the slope of the plasma potential near the subsrate, resulting in changes in flux and energy of the impinging ions across plasma $_strate boundary along themagnetric field. The effect of the substrate DC bias on the low-temperature silicon homoepitaxy (below $560^{\circ}C$) is examine dby in situ reflection high energy electron diffraction (RHEED), cross-section transmission electron microscopy (XTEM),plan-view TEM and high resolution transmision electron microscopy(HRTEM). While the polycrystalline silicon layers are grow withnegative substrate biases, the single crystaline silicon layers are grown with negative substrate biases, the singel crystalline silicon layers are grown with positive substrate biases. As the substrate bias changes form negative to positive values, the growth rate decreases. It is concluded that the control of the ion energy during plasma deposition is very important in silicon epitaxy at low temperatures below $560^{\circ}C$ by UHV-ECRCVD.VD.

• Tribology and Lubricants
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• 제35권1호
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• pp.1-8
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• 2019

Demand for plastic gears are increasing in many industries due to their low production cost, light weight, applicability without lubricant, corrosion resistance and high resilience. Despite these benefits, utilizing plastic gears is limited due to their poor material properties. In this work, DLC coating was applied to improve the tribological properties of polyamide66 gear. 0 V, 40 V, and 70 V of negative bias voltages were selected as a deposition parameter in DC magnetron sputtering system. Pin-on-disk experiment was performed in order to investigate the wear characteristics of the gears. The results of the pin-on-disk experiment showed that DLC coated polyamide66 with 40 V of negative bias voltage had the lowest friction coefficient value (0.134) and DLC coated PA66 with 0 V of negative bias voltage showed the best wear resistance ($9.83{\times}10^{-10}mm^3/N{\cdot}mm$) among all the specimens. Based on these results, durability tests were conducted for DLC coated polyamide66 gears with 0 V of negative bias voltage. The tests showed that the temperature of the uncoated polyamide66 gear increased to about $37^{\circ}C$ while the DLC coated gear saturated at about $25^{\circ}C$. Also, the power transmission efficiency of the DLC coated gear increased by about 6% compared to those without coating. Weight loss of the polyamide66 gears were reduced by about 73%.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2012년도 제43회 하계 정기 학술대회 초록집
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• pp.340-341
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• 2012

In this work, we investigated the effects of temperature stress on flatband voltage (VFB) shifts of HfO2-SiO2 double gate dielectrics devices. Fig. 1 shows a high frequency C-V of the device when a positive bias for 10 min and a subsequent negative bias for 10 min were applied at room temperature (300 K). Fig. 2 shows the corresponding plot when the same positive and negative biases were applied at a higher temperature (473.15 K). These measurements are based on the BTS (bias temperature stress) about mobile charge in the gate oxides. These results indicate that the positive bias stress makes no difference, whereas the negative bias stress produces a significant difference; that is, the VFB value increased from ${\Delta}0.51$ V (300 K, Fig. 1) to ${\Delta}14.45$ V (473.15 K, Fig. 2). To explain these differences, we propose a mechanism on the basis of oxygen vacancy in HfO2. It is well-known that the oxygen vacancy in the p-type MOS-Cap is located within 1 eV below the bottom of the HfO2 conduction band (Fig. 3). In addition, this oxygen vacancy can easily trap the electron. When heated at 473.15 K, the electron is excited to a higher energy level from the original level (Fig. 4). As a result, the electron has sufficient energy to readily cross over the oxide barrier. The probability of trap about oxygen vacancy becomes very higher at 473.15 K, and therefore the VFB shift value becomes considerably larger.

• 한국결정성장학회지
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• 제15권1호
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• pp.10-15
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• 2005

Microwave plasma CVD 다이아몬드/Ti 박막 성장 시 CH₄/H₂ 가스의 유량비율, chuck bias, microwave power 등이 다이아몬드 박막의 구조적 특성과 입자밀도에 미치는 영향에 대하여 조사하였다. 2∼3 CH₄ Vol.% 조건일 때 sp³-결합성의 탄소 neutral 들이 우선적으로 형성되고 sp²-결합성의 탄소 neutral 들이 선택적으로 제거됨에 따라 양질의 다이아몬드 박막을 얻을 수 있었으며, 다이아몬드 입자 증착 기구를 해석하였다. Ti 기판에 걸어준 negative chuck bias가 증가함에 따라 다이아몬드 핵생성이 증진되어 다이아몬드 입자 밀도가 증가하였고, 임계 전압은 약 -50V 임을 확인하였다. 또한, microwave power가 증가함에 따라 미세결정질(micro-crystalline) graphite 층 생성이 제어되고 다이아몬드 층이 형성됨을 확인하였다.

• 한국IT서비스학회지
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• 제21권4호
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• pp.1-26
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• 2022

Recently, the number of cases of purchasing food online has been increased, especially in the open market. Therefore, we examined the characteristics of status quo bias and switching costs in the open market. Also, in this study, the causal relationship between the characteristics of status quo bias and switching costs, switching costs and switching intention in the open market was investigated. The analysis result consists of four parts as follows. First, in the open market, rational decision making, which belongs to the characteristics of status quo bias, was found to have a positive (+) effect on time switching cost among switching costs, but did not have a positive (+) effect on economic and psychological switching cost. Second, cognitive misperceptions was consistent with the assumption that it have a positive (+) effect on all of the economic, time, and psychological switching cost, which are switching costs in the open market. Third, psychological commitment was found to have a positive (+) effect on economic and time switching cost among switching costs, but did not have a positive (+) effect on psychological switching cost. Fourth, psychological switching cost, which belongs to switching costs in the open market, was found to have a negative (-) effect like the hypothesis set in switching intention. However, it was found that economic and time switching cost did not have a negative (-) effect on switching intention. This study subdivided the switching costs into three dimensions and compared the degree of influence on the switching intention, and the degree of influence was different for each dimension. Therefore, it was found that when switching from the existing open market to the new open market, it is not possible to simply judge that the switching costs directly has a negative (-) effect on the switching intention or does not.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2007년도 7th International Meeting on Information Display 제7권1호
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• pp.257-260
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• 2007

Hydrogenated amorphous silicon thin film transistors were fabricated on a flexible metal substrate. A negative voltage at a floated gate can be induced by a negative substrate bias through a capacitor between the substrate and gate electrode. This can recover the shifted-threshold voltage to an original value.

• 한국전기전자재료학회논문지
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• 제16권3호
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• pp.181-185
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• 2003

Influence of post gate oxidation anneal on Negative Bias Temperature Instability (NBTI) of PMOSFE has been investigated. At oxidation anneal temperature raised above 950$^{\circ}$C, a significant improvement of NBTI was observed which enables to reduce PMO V$\_$th/ shift occurred during a Bias Temperature (BT) stress. The high temperature anneal appears to suppress charge generations inside the gate oxide and near the silicon oxide interface during the BT stress. By measuring band-to-band tunneling currents and subthreshold slopes, reduction of oxide trapped charges and interface states at the high temperature oxidation anneal was confirmed.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2000년도 하계학술대회 논문집
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• pp.324-327
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• 2000

In this paper, the effects of negative and positive bias stress on p-channel poly-Si TFT's fabricated by excimer laser annealing have been investigated After positive and negative bias stress, transcon-ductance(g$_{m}$) is increased because of a reduction of the effective channel length due to the injected electron in the gate oxide. In the positive bias stress, the injection of hole is appeared after stress time of 3600sec and g$_{m}$ is decreased. On the other hand, the gate voltage at the maximum g$_{m}$, S-swing and threshold voltage(V$_{th}$) are decreased because of the interface state generation due to the injection of electrons into the gate oxide.e.ide.e.